32 nanometer

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The 32 nanometer (32 nm) process (also called 32 nanometer node) is the next step after the 45 nanometer process in CMOS manufacturing and fabrication. 32 nm refers to the expected average half-pitch of a memory cell at this technology level. The two major chip rivals, Intel and AMD, are both working on a 32 nanometer process for logic, which uses significantly fewer design rules. AMD spent time refining its 45 nm process while researching 22 nm. Intel focused on 32 nm and has already released working samples of processors with hundreds of millions of transistors at 32 nm.^[1] AMD has partnered with IBM on this process, as it did with the 45 nm process. IBM and the Common Platform already has a 32 nm high-k metal gate process available,^[2][3] while Intel has not yet announced a definite time or fab location for its 32 nm process; however, Intel has already given some indications as to the nature of its process and its rough timing for 2009.^[4]

Technology demos

IMEC (Belgium) demonstrated a 32 nm Flash patterning capability based on double patterning and immersion lithography in October 2006.^[5] The introduction of double patterning may offset some of the cost advantages of moving from one node to the next, but may be unavoidable in order to reduce memory cell area.

TSMC similarly used double patterning combined with immersion lithography to produce a 32 nm node 0.183 μm² six-transistor SRAM cell in 2005.^[6]

IBM demonstrated a 0.143 μm² SRAM cell, produced using electron-beam lithography and optical lithography on the same layer. It was observed that the static noise margin (sensitivity to input voltage fluctuations) degraded significantly in going to such a small SRAM cell size. The poly gate pitch was 135 nm.^[7]

Intel showed the first 32 nm test chips to the public on September 18, 2007 at the Intel Developer Forum. At the release, several technical details were disclosed. A second-generation high-k gate dielectric and metal gate were used. The cell size was 0.182 μm² and the chip contained almost 2 billion transistors. 193 nm immersion lithography was used for the critical layers, while 193 nm or 248 nm dry lithography was used on less critical layers.

IM Flash Technologies launched a 32 Gbit NAND Flash built on 34 nm design rules in May 2008. This design rule could only be accomplished with double patterning using 193 nm lithography tools.

In late October 2007, Samsung disclosed a 30 nm NAND Flash patterning process, using self-aligned double patterning. Starting from a 60 nm half-pitch pattern, new material was deposited and etched in between features to produce a 30 nm half-pitch pattern. Presumably, this can be repeated once more for 15 nm half-pitch.

As of 2008, the use of double patterning for 32 nm lithography appears inevitable, due to the lack of availability of alternative lithography techniques which meet manufacturing targets (such as throughput).

The successors to 32 nm technology will be 22 nm, and then 16 nm technology per ITRS.

References

1. ^ Borodovsky, Y. (2006), Proc. SPIE 6153: 615301–615319 
2. ^ Semiconductor International article on IBM alliance offering 32 nm process technology to customers for initial prototyping in Q3 2008
3. ^ Semiconductor International article on IBM Common Platform high-k metal gate 32 nm process already available
4. ^ EETimes article on Intel's 32 nm lithography vendor decision
5. ^ IMEC demonstrates feasibility of double patterning immersion litho for 32nm node:
6. ^ H-Y. Chen et al., Symp. on VLSI Tech. 2005.
7. ^ D. M. Fried et al., IEDM 2004.

Further reading

• S. Steen et al., Microelec. Eng., vol. 83, pp. 754-761 (2006).

External links

• Chipmakers gear up for manufacturing hurdles
• Sony, IBM, and Toshiba partnering on semiconductor research
• IBM and AMD partnering on semiconductor research
• Slashdot discussion
• Intel press release
• Intel 32 nm process
• Intel 32 nm SRAM demonstration at IDF 2007
• Samsung self-aligned double patterning technology