A barrel processor is a CPU that switches between threads of execution on every cycle. This CPU design technique is also known as "interleaved" or "fine-grained" temporal multithreading. As opposed to simultaneous multithreading in modern superscalar architectures, it generally does not allow execution of multiple instructions in one cycle.
For example, the peripheral processing system of the CDC 6000 series computers and its successors executed one instruction (or a portion of an instruction) from each of 10 different virtual processors (called peripheral processors) before returning to the first processor[1]. Also, the IP3023 processor from Ubicom executes one instruction from each of 8 different threads before returning to the first thread.
Like preemptive multitasking, each thread of execution is assigned its own program counter and other hardware registers (each thread's architectural state). A barrel processor can guarantee that each thread will execute 1 instruction every N cycles, unlike a preemptive multitasking machine, that typically runs one thread of execution for hundreds or thousands of cycles, while all other threads wait their turn.
A technique called C-slowing can take a normal single-tasking processor design and automatically generate a corresponding barrel processor design. An n-way barrel processor generated this way acts much like n separate multiprocessing copies of the original single-tasking processor, each one running at roughly 1/n the original speed.
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Advantages compared to single threaded processors
A single-tasking processor spends a lot of time waiting around, not doing anything useful whenever a cache miss or pipeline stall occurs. Advantages to employing barrel processors over single-tasking processors include:
- The ability to do useful work on the other threads while the stalled thread is waiting.
- Designing an n-way barrel processor with n-deep pipelines is much simpler than designing a single-tasking processor because a barrel processor never has a pipeline stall and doesn't need feed-forward circuits.
- For real-time applications, a barrel processor can guarantee that a "real-time" thread can execute with precise timing, no matter what happens to the other threads -- even if some other thread locks up in an infinite loop or is continuously interrupted by hardware interrupts.
Disadvantages compared to single threaded processors
There are, however, some disadvantages to barrel processors.
- Either all threads must share the same cache, which slows overall system performance, or there must be one unit of cache for each execution thread, which can significantly increase the transistor count (and thus cost) of such a CPU. However, most barrel processors are used to implement hard real time embedded systems, where memory access costs are typically calculated assuming worst-case behavior of the cache, so this is less of a concern.
- The state of each thread must be kept on-chip (typically in registers) to avoid costly off-chip context switches. This requires a large number of registers compared to typical processors.
References
- ^ CDC Cyber 170 Computer Systems; Models 720, 730, 750, and 760; Model 176 (Level B); CPU Instruction Set; PPU Instruction Set -- See page 2-44 for an illustration of the rotating "barrel".
See also
External links
- Soft peripherals Embedded.com article examines Ubicom's IP3023 processor
- An Evaluation of the Design of the Gamma 60
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