A control register is a processor register which changes or controls the general behavior of a CPU or other digital device. Common tasks performed by control registers include interrupt control, switching the addressing mode, paging control, and coprocessor control.
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Control registers in x86 series
CR0
The CR0 register is 32 bits long on the 386 and higher processors. On x86-64 processors in long mode, it (and the other control registers) are 64 bits long. CR0 has various control flags that modify the basic operation of the processor.
| Bit | Name | Full Name | Description |
|---|---|---|---|
| 31 | PG | Paging | If 1, enable paging and use the CR3 register, else disable paging |
| 30 | CD | Cache disable | Globally enables/disable the memory cache |
| 29 | NW | Not-write through | Globally enables/disable write-back caching |
| 18 | AM | Alignment mask | Alignment check enabled if AM set, AC flag set (in EFLAGS register, and privilege level is 3) |
| 16 | WP | Write protect | Determines whether the CPU can write to pages marked read-only |
| 5 | NE | Numeric error | Enable internal x87 floating point error reporting when set, else enables PC style x87 error detection |
| 4 | ET | Extension type | On the 386, it allowed to specify whether the external math coprocessor was an 80287 or 80387 |
| 3 | TS | Task switched | Allows saving x87 task context only after x87 instruction used after task switch |
| 2 | EM | Emulation | If set, no x87 floating point unit present, if clear, x87 FPU present |
| 1 | MP | Monitor co-processor | Controls interaction of WAIT/FWAIT instructions with TS flag in CR0 |
| 0 | PE | Protected Mode Enable | If 1, system is in protected mode, else system is in real mode |
CR1
Reserved
CR2
Contains a value called Page Fault Linear Address (PFLA). When a page fault occurs, the address the program attempted to access is stored in the CR2 register.
CR3
Used when virtual addressing is enabled, hence when the PG bit is set in CR0. CR3 enables the processor to translate virtual addresses into physical addresses by locating the page directory and page tables for the current task. Typically, the upper 20 bits of CR3 become page directory base register (PDBR).
CR4
Used in protected mode to control operations such as virtual-8086 support, enabling I/O breakpoints, page size extension and machine check exceptions.
| Bit | Name | Full Name | Description |
|---|---|---|---|
| 14 | SMXE | SMX Enable | |
| 13 | VMXE | VMX Enable | |
| 10 | OSXMMEXCPT | Operating System Support for Unmasked SIMD Floating-Point Exceptions | enable unmasked SSE exceptions |
| 9 | OSFXSR | Operating system support for FXSAVE and FXSTOR instructions | Must be set to use SSE instructions, enable fast FPU save and restore |
| 8 | PCE | Performance-Monitoring Counter enable | If set, RDPMC can be executed at any privilege level, else it can only be used in kernel mode (ring 0) |
| 7 | PGE | Page Global Enabled | |
| 6 | MCE | Machine Check Exception | Enables machine check interrupts to occur if set |
| 5 | PAE | Physical Address Extension | Changes page table layout to translate 32-bit virtual address into extended 36-bit physical address |
| 4 | PSE | Page Size Extensions | If unset page size is 4 KiB, else it is increased to 4 MiB, or with PAE, 2 MiB |
| 3 | DE | Debugging Extensions | |
| 2 | TSD | Time Stamp Disable | If set, RDTSC instruction can only be executed when in ring 0, otherwise RDTSC can be used at any privilege level |
| 1 | PVI | Protected-mode Virtual Interrupts | Enables hardware support of virtual interrupt flag (VIF) in protected mode.This feature can enable some program running at privilege level 0 to run at privilege level 3(applications level;least privileged) |
| 0 | VME | Virtual 8086 Mode Extensions | If set,enables support for virtual interrupt flag in virtual-8086 mode.This feature may improve performance in this mode |
Additional Control registers in x86-64 series
EFER
Extended Feature Enable Register (EFER) is a register added in the AMD K6 processor, to allow enabling the SYSCALL/SYSRET instruction, and later for entering and exiting long mode.
| Bit | Purpose |
|---|---|
| 63:12 | Reserved |
| 11 | Execute-disable bit enable (NXE) |
| 10 | IA-32e mode active (LMA) |
| 9 | Reserved |
| 8 | IA-32e mode enable (LME) |
| 7:1 | Reserved |
| 0 | SysCall enable (SCE) |
See also
- Protected mode in x86 Assembly at Wikibooks
- General purpose registers
- Test register
- Debug register
- Flag byte
- Status register
References
External links
- Intel IA-32 Architecture Software Developer’s Manuals
- AMD64 Architecture Tech Docs
- Cracking Open The Pentium III
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