The CVT16 instruction set, announced by AMD on May 1, 2009, is an extension to the 128-bit SSE core instructions in the X86 and AMD64 instruction set for the Bulldozer processor core, due to begin production in 2011[1].
CVT16 is a revision of part of the SSE5 instruction set proposal announced on August 30, 2007. This revision makes the binary coding of the proposed new instructions more compatible with Intel's AVX instruction extensions, while the functionality of the instructions is unchanged.
The CVT16 instructions allow conversion of floating point vectors between single precision and half precision.
The CVT16 instruction set is supplemented by the XOP and FMA4 instruction sets, which were also included in SSE5.
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