Cycle stealing

Cycle stealing is used to describe the "stealing" of a single CPU cycle to allow a DMA engine to perform a DMA operation. This is opposed to block operation where a DMA engine would request a bus, hold it for a complete transaction (typically 16-32 bytes but could last much longer) before releasing to a CPU.

Cycle stealing generally occurs when the entire DMA transfer of data is finished, the DMA controller interrupts the CPU.

Modern architecture

This term is less common in modern computer architecture (say above 66-100 MHz), where the various external buses and controllers generally run at different rates, and CPU internal operations are no longer closely coupled to I/O bus operations.

Background note

Cycle stealing has been the cause of major performance degradation on machine such as the Sinclair QL, where, for economy reasons, the video RAM was not dual access. Consequently, the M68008 was denied access to the memory bus when the ZX8301 was accessing memory, and the machine performed poorly when compared with machines using similar processors at similar speeds.

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