DDR2 SDRAM

Two PC2-6400 modules encased in heat spreaders

PC2-6400 DDR2 SO-DIMM (for notebooks)

DDR2 SDRAM is a double data rate synchronous dynamic random access memory interface. It supersedes the original DDR SDRAM specification and the two are not compatible. In addition to double pumping the data bus as in DDR SDRAM, (transferring data on the rising and falling edges of the bus clock signal), DDR2 employs an I/O buffer between the memory and the data bus so that the data bus can be run at twice the speed of the memory clock. The two factors combine to achieve a total of 4 data transfers per memory clock cycle.

With data being transferred 64 bits at a time, DDR2 SDRAM gives a transfer rate of (memory clock rate) × 2 (for bus clock multiplier) × 2 (for dual rate) × 64 (number of bits transferred) / 8 (number of bits/byte). Thus with a memory clock frequency of 100 MHz, DDR2 SDRAM gives a maximum transfer rate of 3200 MB/s.

Since the memory clock runs at half the external data bus clock rate, DDR2 memory operating at the same external data bus clock rate as DDR will provide the same bandwidth but with higher latency, resulting in inferior performance. Alternatively, DDR2 memory operating at twice the external data bus clock rate as DDR may provide twice the bandwidth with the same latency (in nanoseconds). The best-rated DDR2 memory modules are at least twice as fast as the best-rated DDR memory modules.

Overview

Like all SDRAM implementations, DDR2 stores memory in memory cells that are activated with the use of a clock signal to synchronize their operation with an external data bus. Like DDR before it, DDR2 cells transfer data both on the rising and falling edge of the clock (a technique called "double pumping"). The key difference between DDR and DDR2 is that in DDR2 the bus is clocked at twice the rate of the memory cells, so four bits of data can be transferred per memory cell cycle. Thus, without changing the memory cells themselves, DDR2 can effectively operate at twice the data rate of DDR.

DDR2's bus frequency is boosted by electrical interface improvements, on-die termination, prefetch buffers and off-chip drivers. However, latency is greatly increased as a trade-off. The DDR2 prefetch buffer is 4 bits deep, whereas it is 2 bits deep for DDR and 8 bits deep for DDR3. While DDR SDRAM has typical read latencies of between 2 and 3 bus cycles, DDR2 may have read latencies between 4 and 6 cycles. Thus, DDR2 memory must be operated at twice the data rate to achieve the same latency.

Another cost of the increased bandwidth is the requirement that the chips are packaged in a more expensive and more difficult to assemble BGA package as compared to the TSSOP package of the previous memory generations such as DDR SDRAM and SDR SDRAM. This packaging change was necessary to maintain signal integrity at higher bandwidths.

Power savings are achieved primarily due to an improved manufacturing process through die shrinkage, resulting in a drop in operating voltage (1.8 V compared to DDR's 2.5 V). The lower memory clock frequency may also enable power reductions in applications that do not require the highest available data rates.

According to JEDEC^[1] the maximum recommended voltage is 1.9 volts and should be considered the absolute maximum when memory stability is an issue (such as in servers or other mission critical devices). In addition, JEDEC states that memory modules must withstand up to 2.3 volts before incurring permanent damage (although they may not actually function correctly at that level).

Specification standards

Chips and modules

For use in computers, DDR2 SDRAM is supplied in DIMMs with 240 pins and a single locating notch. Laptop DDR2 SO-DIMMs have 200 pins. DIMMs are identified by their peak transfer capacity (often called bandwidth).

Note: DDR2-xxx denotes data transfer rate, and describes raw DDR chips, whereas PC2-xxxx denotes theoretical bandwidth (though it is often rounded up or down), and is used to describe assembled DIMMs. Bandwidth is calculated by taking transfers per second and multiplying by eight. This is because DDR2 memory modules transfer data on a bus that is 64 data bits wide, and since a byte comprises 8 bits, this equates to 8 bytes of data per transfer.

¹ Some manufacturers label their DDR2 modules as PC2-4300 instead of PC2-4200, PC2-5400 instead of PC2-5300 and PC2-8600 instead of PC2-8500. At least one manufacturer has reported this reflects successful testing at a higher-than standard data rate^[4] whilst others simply use the alternate rounding as the name, as described above.

In addition to bandwidth and capacity variants, modules can

1. Optionally implement ECC, which is an extra data byte lane used for correcting minor errors and detecting major errors for better reliability. Modules with ECC are identified by an additional ECC in their designation. PC2-4200 ECC is a PC2-4200 module with ECC.
2. Be "registered", which improves signal integrity (and hence potentially clock rates and physical slot capacity) by electrically buffering the signals at a cost of an extra clock of increased latency. Those modules are identified by an additional R in their designation, whereas non-registered (a.k.a. "unbuffered") RAM may be identified by an additional U in the designation. PC2-4200R is a registered PC2-4200 module, PC2-4200R ECC is the same module but with additional ECC.
3. Be fully buffered modules, which are designated by F or FB and do not have the same notch position as other classes. Fully buffered modules cannot be used with motherboards that are made for registered modules, and the different notch position physically prevents their insertion.

Note: registered and un-buffered SDRAM generally cannot be mixed on the same channel.

Note that the highest-rated DDR2 modules in 2009 operate at 533 MHz (1066 MT/s), compared to the highest-rated DDR modules operating at 200 MHz (400 MT/s). At the same time, the CAS latency of 11.2 ns = 6 / (Bus clock rate) for the best PC2-8500 modules is comparable to that of 10 ns = 4 / (Bus clock rate) for the best PC-3200 modules.

Debut

DDR2 was introduced in the second quarter of 2003 at two initial clock rates: 200 MHz (referred to as PC2-3200) and 266 MHz (PC2-4200). Both performed worse than the original DDR specification due to higher latency, which made total access times longer. However, the original DDR technology tops out at a clock rate around 200 MHz (400 MT/s). Higher performance DDR chips exist, but JEDEC has stated that they will not be standardized. These modules are mostly manufacturer optimizations of highest-yielding chips, drawing significantly more power than slower-clocked modules, and usually do not offer much, if any, greater real-world performance.

DDR2 started to become competitive with the older DDR standard by the end of 2004, as modules with lower latencies became available.^[5]

Backward compatibility

DDR2 DIMMs are not designed to be backward compatible with DDR DIMMs. The notch on DDR2 DIMMs is in a different position from DDR DIMMs, and the pin density is higher than DDR DIMMs in desktops. DDR2 is a 240-pin module, DDR is a 184-pin module. Notebooks have 200-pin modules for DDR and DDR2, however the notch on DDR modules is in a slightly different position than that on DDR2 modules.

Higher performance DDR2 DIMMs are compatible with lower performance DDR2 DIMMs; however, the higher performance module runs at the lower module's frequency. Using lower performing DDR2 memory in a system capable of higher performance results in the bus running at the rate of the lowest performance memory in use.

See also

• CAS latency (definition of "CAS 5-5-5-15", for example)
• Dual-channel architecture
• Fully Buffered DIMM
• SO-DIMM
• Unbuffered memory
• List of device bandwidths

References

Further reading

• JEDEC standard: DDR2 SDRAM Specification
• JEDEC standard: DDR2-1066
• "JEDEC Standard No. 21C: 4.20.13 240-Pin PC-3200/PC2-4200/PC2-5300/PC2-6400 DDR2 SDRAM Unbuffered DIMM Design Specification" (PDF). JEDEC Solid State Technology Association. 2005-01-05. http://www.jedec.org/download/search/4_20_13R15.pdf. Retrieved 2007-10-07. 
• Razak Mohammed Ali. "DDR2 SDRAM interfaces for next-gen systems" (PDF). Electronic Engineering Times. http://www.eetasia.com/ARTICLES/2006OCT/PDF/EEOL_2006OCT16_INTD_STOR_TA.pdf. 

External links

• JEDEC website
• Overview of DDR-II technology
• DDR2 low latency vs high bandwidth, Conroe performance