Emitter-coupled logic

Motorola ECL 10,000 basic gate circuit diagram^[1]

In electronics, emitter-coupled logic, or ECL, is a logic family that achieves high speed by using an overdriven BJT differential amplifier with limited emitter current to avoid the slow saturation region of transistor operation.^[2] As the current is steered between the two legs of the emitter-coupled pair, ECL is sometimes called current-steering logic (CSL),^[3] current-mode logic (CML)^[4] or current-switch emitter-follower (CSEF) logic.^[5]

In ECL the transistors are never in saturation, the input/output voltages have a small swing (0.8 V), and the output resistance is generally low; as a result, the transistors change states quickly and gate delays are low. In addition, the complementary outputs decrease the propagation time of the whole circuit by saving additional inverters. ECL's major disadvantage is that the circuit continuously draws current, which means it requires a lot of power.

The equivalent of emitter-coupled logic made out of FETs is called source-coupled FET logic (SCFL).^[6]

History

Yourke's current switch, c. 1955.^[7]

ECL was invented in August 1956 at IBM by Hannon S. Yourke.^[8][9] Originally called current steering logic, it was used in the Stretch, IBM 7090, and IBM 7094 computers.^[7]

While ECL circuits in the mid-1960s through the 1990s consisted of a differential amplifier input stage to perform logic, followed by an emitter follower to drive outputs and shift the output voltages so they will be compatible with the inputs, Yourke's current switch, also known as ECL, consisted only of differential amplifiers. To provide compatible input and output levels, two complementary versions were used, an NPN version and a PNP version. The NPN output could drive PNP inputs, and vice-versa. "The disadvantages are that more different power supply voltages are needed, and both pnp and npn transistors are required."^[7]

Motorola introduced their first digital monolithic integrated circuit line, MECL I, in 1962.^[10]

The drawbacks associated with ECL have meant that it has been used mainly when high performance is a vital requirement. Older high-end mainframe computers, such as the Enterprise System/9000 members of IBM's ESA/390 computer family, used ECL;^[11] current IBM mainframes use CMOS.

Implementation

In this schematic, transistor T5' represents the output transistor of a previous ECL gate that provides a logic signal to input transistor T1 of an OR/NOR gate whose other input is at T2 and has outputs Y and Y. The figure shows what the voltages are and where currents flow in typical ECL at high input voltage (logical "1"). The output emitter resistors R_E4 and R_E5 are included to close the current loops tidily on the circuit diagram; they do not exist in all versions of ECL. In some cases line termination 50 Ω resistors connected between the bases of the input transistors and -2 V act as emitter resistors.^[12]

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ECL is based on an emitter-coupled (long-tailed) pair acting as a current-steering switch where transistors are either cut off or in the active linear region, depending on the state of the circuit (see the figure on the right). The left part consists of parallel-connected input transistors T1 and T2 (for the exemplary two-input gate) implementing NOR logic. The base voltage of the right transistor T3 is held fixed at V_REF = -1.3 V by a reference voltage source – the voltage divider R₁–R₂ with a diode thermal compensation and sometimes a buffering emitter follower (non-shown on the picture) provide the base reference voltage; thus the emitter voltages are kept relatively steady. The emitter current is limited by a current source (the resistor R_E). Because of the relatively steady emitter voltage, the common emitter resistor acts nearly as a current source. The output voltages at the collector load resistors R_C1 and R_C3 are shifted and buffered to the inverting and non-inverting outputs by the emitter followers T4 and T5.

The circuit has low voltage V_L = -1.7 V and high voltage V_H = -0.9 V that are situated symmetrically (±0.4 V) with respect to the reference voltage V_REF.

The "long tail" current source (R_E) sets the total current flowing through the two legs (T1 and T2 from the left side and T3 from the right side). The input logic voltages control the current flowing through the input transistors by sharing that current between the two legs, steering it all to one side when not near the switching point. To prevent saturation of the input transistors, the resistances R_E and R_C1 are defined so that at maximum input voltage the total voltage drop across these resistors is less than the voltage supply V_EE, leaving some voltage across the transistor. When any input is high, the input leg (T1 or T2) takes all the current, starving the reference leg (T3) which becomes cut-off.

A bias configuration supplies a constant voltage at the midrange of the low and high logic levels to the reference side of the differential amplifier, so that the appropriate logical function of the input voltages will control the amplifier's current switching. Diodes D1 and D2 compensate the thermal variations of the BJTs, keeping the amplifier reasonably balanced. The output emitter followers T4 and T5 shift the collector voltage levels and provide low output resistance.

Characteristics

Other noteworthy characteristics of the ECL family include the fact that the large current requirement is approximately constant, and does not depend significantly on the state of the circuit. This means that ECL circuits generate relatively little power noise, unlike many other logic types which typically draw far more current when switching than quiescent, for which power noise can become problematic. In cryptographic applications, ECL circuits are also less susceptible to side channel attacks such as differential power analysis.

The propagation time for this arrangement can be less than a nanosecond, making it for many years the fastest logic family.

Power supplies and logic levels

The ECL circuits usually operate with negative power supplies (positive end of the supply is connected to ground) in contrast to other logic families in which negative end of the supply is grounded. This is done mainly to minimize the influence of the power supply variations on the logic levels as ECL is more sensitive to noise on the V_CC and relatively immune to noise on V_EE^[13]. Because ground should be the most stable voltage in a system, ECL is specified with a positive ground. In this connection, when the supply voltage varies, the currents flowing through the collector resistors change slightly and the voltage drops across the collector resistors stay almost constant although the voltage divider R1-R2 compensates the voltage variations to some extent. As the collector resistors are firmly "tied up" to ground, the collector (output) voltages do not "move". If the negative end of the power supply was grounded, the collector resistors would be attached to the positive rail. As the constant voltage drops across the collector resistors stay relatively constant, the collector (output) voltages follow the supply voltage variations and the two circuit parts act as constant current level shifters (although, in this case, the voltage divider R1-R2 compensates the voltage variations more significantly). The positive power supply has another disadvantage - the output voltages will vary slightly (±0.4 V) against the background of high constant voltage (+3.9 V). Another reason for using a negative power supply is protection of the output transistors from an accidental short circuit developing between the output and ground^[14] (but the outputs are not protected from a short circuit with the negative rail).

The value of the supply voltage is choosen so that a sufficient current to flow through the compensating diodes D1 and D2 and the voltage drop across the common emitter resistor R_E to be adequate.

ECL circuits available on the open market usually operated with logic levels incompatible with other families. This meant that interoperation between ECL and other logic families, such as the popular TTL family, required additional interface circuits. The fact that the high and low logic levels are relatively close meant that ECL suffers from small noise margins, which can be troublesome.

At least one manufacturer, IBM, made ECL circuits for use in the manufacturer's own products; the power supplies were substantially different from those used in the open market.^[11]

See also

• Long-tailed pair
• Resistor–transistor logic (RTL)
• Diode–transistor logic (DTL)
• Transistor–transistor logic (TTL)
• Complementary metal–oxide–semiconductor (CMOS)
• Positive emitter-coupled logic (PECL)
• Low-voltage positive emitter-coupled logic (LVPECL)
• Integrated injection logic (I2L)

References

External links

• Emitter-coupled logic at play-hookey.com
• Motorola MECL logic family datasheets, 1963
• ECL logic levels
• Presenting the emitter-coupled circuits as a system of two interacting negative feedback systems