(Electrically Erasable PLD) A programmable logic device (PLD) that uses EEPROM to store its logic design interconnections. EEPROM-based electrically erasable PLDs and EPROM-based "erasable" PLDs are often used in the testing stages of a new chip design. When the design has been thoroughly tested, less expensive one-time programmable PLDs may be used for the final product. See PLD.
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