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Half subtractor

 
Wikipedia: Half subtractor

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Half Subtractor

Logic diagram for a half subtractor

The half-subtractor is a combinational circuit which is used to perform subtraction of two bits. It has two inputs, X (minuend) and Y (subtrahend) and two outputs D (difference) and B (borrow).

Truth Table

The truth table for the half subtractor is given below. [1]

X Y D B
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

From the above table one can draw the Karnaugh map for "difference" and "borrow".

Full Subtractor

The Full_subtractor is a combinational circuit which is used to perform subtraction of three bits. It has two inputs, X (minuend) and Y (subtrahend and Z ([[subtrahend]) and two outputs D (difference) and B (borrow).

Truth Table

The truth table for the full subtractor is given below. [2]

X Y Z D B
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

So, Logic equations are D = (X xor Y)xor Z, B = (Z and (not(X xor Y)))or ((not X)and Y)

References

  1. ^ ""Subtraction using Logic gates"". http://www.shef.ac.uk/physics/teaching/phy107/logicsub.html. 
  2. ^ ""Subtraction using Logic gates"". http://www.shef.ac.uk/physics/teaching/phy107/logicsub.html. 

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