Depletion-load NMOS logic

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Depletion-load NMOS (n-channel metal-oxide-semiconductor), in many cases labeled HMOS for "high performance," is a digital circuit style which uses n-type MOSFETs to implement logic gates. It is based on enhancement-load NMOS logic technology, achieving greater speed at higher manufacturing cost. The performance gain, and price increase, derive from the inclusion of depletion-mode NMOS transistors in the manufacturing process. These transistors are tuned to be better ideal current sources.

Such processes were the state of the art in the late 1970s, being used to make the Intel 8086 and Motorola 68000. Requiring at least two lithographic doping steps versus one for enhancement-mode NMOS and three for CMOS, they fell between these two technology generations. All NMOS was superseded by CMOS in the early 1980s.

Depletion-mode transistors are formed by increasing the amount of dopant in the channel region. Both NMOS and HMOS are obsolete, as they implement power-draining short circuits in steady state. CMOS technology eliminates all but transient short circuits.

Evolution from preceding NMOS logic

Depletion-load processes differ from their predecessors in the way the Vdd voltage source, representing 1, connects to each gate. In both technologies, each gate contains one NMOS transistor which is permanently turned on and connected to Vdd. When the transistors connecting to 0 turn off, this pull-up transistor determines the output to be 1 by default. In standard NMOS, the pull-up is the same kind of transistor as is used for logic switches. As the output voltage approaches a value less than Vdd, it gradually switches itself off. This slows the 0 to 1 transition, resulting in a slower circuit. Depletion-load processes replace this transistor with a depletion-mode NMOS at a constant gate bias, with the gate tied directly to the source. This alternative type of transistor acts as a current source until the output approaches 1, then acts as a resistor. The result is a faster 0 to 1 transition.

Static power consumption

Depletion-load circuits consume less power than enhancement-load circuits at the same speed. In both cases the connection to 1 is always active, even when the connection to 0 is also active. This results in a short circuit, wasting power. The amount of waste depends on the strength, or physical size, of the pull-up. Both normal (enhancement-mode) and depletion-mode pull-up transistors use greatest power when the output is stable at 0, so this loss is considerable. The sizes of the pull-ups are thus adjusted so that the 0 to 1 transition speed matches the 1 to 0 speed, but no more, as that would waste power. Because the strength of a depletion-mode transistor falls off less on the approach to 1, they may reach 1 faster despite starting slower, i.e. conducting less current at the beginning of the transition and at steady state.