(Intel Architecture-64) The 64-bit architecture used in Intel's Itanium family of CPU chips. Designed for fast parallel instruction execution, IA-64 was created at the end of the 20th century, whereas IA-32 chips (x86-based CPUs) date back to the early 1970s when designs were based on a fraction of the number of transistors that are placed on chips today. See Itanium and x86.
IA-32 Has 64 Bits Too
Subsequent to IA-64, Intel added 64-bit extensions to its x86-based Pentium (IA-32) line, known as "Intel 64" (first called "EM64T"). However, IA-64 is more advanced and was designed for greater future capabilities. See Intel 64.
Recompilation Is Required
Although applications written for x86 and HP 9000 computers run intact on IA-64 machines via translation layers (see
Rather than variable-length instructions as in IA-32, IA-64 uses fixed-length, four-byte instructions bundled in sets of three "long instruction words." IA-64 uses 256 registers for integer and floating point operations compared to 16 in IA-32.
IA-64 Predicts the Future
To take advantage of an advanced pipeline architecture, IA-64 employs "predication." Both sides of a branch instruction following a compare are executed in parallel. After determining which branch is correct, the results of the other are discarded. IA-64 compilers have to set up the predication; they have to interleave the instructions and add codes that tell the CPU how to execute in parallel. If predication is not set up, the CPU performs a simpler prediction, whereby it executes in parallel the side of the branch that it thinks will be the outcome, not both sides. If it guesses wrong, the parallelism is lost for those few nanoseconds.
IA-64 also supports speculative loading, which loads data into registers before the instructions actually need to process it. Intel brands this parallel architecture "Explicitly Parallel Instruction Computing" (EPIC), and sometimes refers to the IA-64 architecture as EPIC; thus, IA-64 and EPIC are synonymous.
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