Latchup is a term used in the realm of integrated circuits (microchips) to describe a particular type of short circuit which can occur in an improperly designed circuit. More specifically it is the inadvertent creation of a low-impedance path between the power supply rails of a MOSFET circuit, triggering a parasitic structure which disrupts proper functioning of the part and possibly even leading to its destruction due to overcurrent. A power cycle is required to correct this situation.
The parasitic structure is usually equivalent to a thyristor (or SCR), a PNPN structure which acts as a PNP and an NPN transistor stacked next to each other. During a latchup when one of the transistors is conducting, the other one begins conducting too. They both keep each other in saturation for as long as the structure is forward-biased and some current flows through it - which usually means until a power-down. The SCR parasitic structure is formed as a part of the totem-pole PMOS and NMOS transistor pair on the output drivers of the gates.
The latchup does not have to happen between the power rails; it can happen at any place where the required parasitic structure exists. A spike of positive or negative voltage on an input or output pin of a digital chip, exceeding the rail voltage by more than a diode drop, is a common cause of latchup. Another cause is the supply voltage exceeding the absolute maximum rating, often from a transient spike in the power supply, leading to a breakdown of some internal junction. This frequently happens in circuits which use multiple supply voltages that do not come up in the proper order after a power-up, leading to voltages on data lines exceeding the input rating of parts that have not yet reached a nominal supply voltage.
Yet another common cause of latchups is ionizing radiation.
It is possible to design chips that are latchup-resistant, where a layer of insulating oxide (called a trench) surrounds both the NMOS and the PMOS transistors. This breaks the parasitic SCR structure between these transistors. Such parts are important in the cases where the proper sequencing of power and signals cannot be guaranteed (e.g., in hot swap devices). Most silicon-on-insulator devices are inherently latchup-resistant.
Devices fabricated in lightly doped epitaxial layers grown on heavily doped substrates are also less susceptible to latchup. The heavily doped layer acts as a current sink where excess minority carriers can quickly recombine.
Another possibility for a latchup prevention is the Latchup Protection Technology circuit. When a latchup is detected, the LPT circuit shuts down the chip and holds it powered-down for a preset time.
Testing for Latchup
- See EIA/JEDEC STANDARD IC Latch-Up Test EIA/JESD78.
This standard is commonly referenced in IC qualification specifications.
See also
- Electrostatic discharge: For qualification testing of semiconductor devices, ESD and latchup are commonly considered together.
External links
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