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It has been suggested that this article or section be merged with SDRAM latency. (Discuss) |
Memory timings (or RAM timings) refer collectively to a set of four numerical parameters called CL, tRCD, tRP, and tRAS, commonly represented as a series of four numbers separated with dashes, in that respective order (e.g. 5-5-5-15). However, it is not unusual for tRAS to be omitted, or for a fifth value, the Command rate, to be added on. It also remains a common practice to advertise only CL. These parameters define, in clock cycles, the various forms of latency (responsiveness to random requests) that affect fundamental performance metrics of random access memory. Lower ("tight") timings imply better performance.
Modern DIMMs include a Serial Presence Detect (SPD) RAM that contains recommended memory timings for automatic configuration. The BIOS on a PC may allow the user to make adjustments in an effort to increase performance (with possible risk of decreased stability) or, in some cases, to increase stability (by lowering performance).
Memory timings are distinct from memory bandwidth; the latter measures the throughput of memory. It is possible for an advance in memory technology to increase both bandwidth (an apparent performance improvement) and latency (an apparent performance degradation). For example, DDR memory has been superseded by DDR2, and yet DDR2 has significantly higher latency at the same clock frequencies. However, DDR2 can be clocked faster, decreasing its cycle time; DDR2 clocked significantly higher than DDR also has lower latency (in nanoseconds) than DDR.
| Name | Symbol | Definition |
|---|---|---|
| CAS latency | CL | The time between sending a column address to the memory and the beginning of the data in response. This is the time it takes to read the first bit of memory from a DRAM with the correct row already open. |
| Row Address to Column Address Delay | TRCD | The number of clock cycles required between the opening a row of memory and accessing columns within it. The time to read the first bit of memory from a DRAM without an active row is TRCD + CL. |
| Row Precharge Time | TRP | The number of clock cycles required between the issuing of the precharge command and opening the next row. The time to read the first bit of memory from a DRAM with the wrong row open is TRP + TRCD + CL. |
| Row Active Time | TRAS | The number of clock cycles required between a bank active command and issuing the precharge command. This is the time needed to internally refresh the row, and overlaps with TRCD. Typically approximately equal to the sum of the previous three numbers. |
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