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| INPUT A B |
OUTPUT A NOR B |
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| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 0 |
The NOR gate is a digital logic gate that implements logical NOR - it behaves according to the truth table to the right. A HIGH output (1) results if both the inputs to the gate are LOW (0). If one or both input is HIGH (1), a LOW output (0) results. NOR is the result of the negation of the OR operator. NOR is a functionally complete operation -- combinations of NOR gates can be combined to generate any other logical function. By contrast, the OR operator is monotonic as it can only change LOW to HIGH but not vice versa.
In most, but not all, circuit implementations, the negation comes for free -- including CMOS and TTL. In such logic families, the only way to implement OR is with 2 or more gates, such as a NOR followed by an inverter. A significant exception is some forms of the domino logic family.
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There are three symbols for NOR gates: the American (ANSI or 'military') symbol and the IEC ('European' or 'rectangular') symbol, as well as the deprecated DIN symbol. For more information see Logic Gate Symbols.
| MIL/ANSI Symbol | IEC Symbol | DIN Symbol |
NOR Gates are basic logic gates, and as such they are recognised in TTL and CMOS ICs. The standard, 4000 series, CMOS IC is the 4001, which includes four independent, two-input, NOR gates. The pinout diagram is as follows:
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Pinout Diagram of a 4001 Quad NOR DIL-format IC
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1 Input A1 2 Input B1 3 Output Q1 4 Output Q2 5 Input B2 6 Input A2 7 VSS 8 Input A3 9 Input B3 10 Output Q3 11 Output Q4 12 Input B4 13 Input A4 14 VDD |
These devices are available from most semiconductor manufacturers such as Fairchild Semiconductor, Philips or Texas Instruments. These are usually available in both through-hole DIP and SOIC format. Datasheets are readily available in most datasheet databases.
The standard 2-, 3-, 4- and 8-input NOR gates are available:
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The physical layout of a CMOS NOR
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This diagrams above show the construction of a 2-input NOR gate using NMOS circuitry. If either of the inputs are high, the corresponding NMOS is turned on and the output is pulled low; otherwise the output is pulled high through the pull-up resistor. The diagram below shows a 2-input NOR gate using CMOS technology. The diodes and resistors on the inputs are to protect the CMOS components from damage due to electrostatic discharge (ESD) and play no part in the logical function of the circuit.
If no specific NOR gates are available, one can be made from NAND gates in the configuration shown below. Interestingly, any logic gate can be made either from a combination of NAND gates or from a combination of NOR gates.
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![]() | Dictionary. The American Heritage® Dictionary of the English Language, Fourth Edition Copyright © 2007, 2000 by Houghton Mifflin Company. Updated in 2009. Published by Houghton Mifflin Company. All rights reserved. Read more | |
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