In electronic design automation, parasitic extraction is calculation of the parasitic effects in the interconnects of an electronic circuit: parasitic capacitances, parasitic resistances and parasitic inductances, commonly called parasitic devices, parasitic components, or simply parasitics.
Major purposes of parasitic extraction are signal delay calculation, timing analysis, circuit simulation, and signal integrity analysis.
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Background
In early integrated circuits the impact of the wiring was negligible, and wires were not considered as electrical elements of the circuit. However below the 0.5-micron technology node resistance and capacitance of the interconnects started making a significant impact on circuit performance. [1] With shrinking process technologies inductance effects of interconnects became important as well.
Major effects of interconnect parasitics include signal delay and signal noise.
Interconnect capacitance extraction
Interconnect resistance extraction
Interconnect inductance extraction
Tools and vendors
The tools fall into the following broad categories.
- Field solvers provide physically accurate solutions. They calculate electromagnetic parameters by directly solving Maxwell's equations. Due to high calculation burden they are applicable only very small designs or to parts of the designs.
- Approximate solutions with pattern matching tecniques are the only feasible approach to extract parasitics for complete modern integrated circuit designs.
FastCap, FastHenry
FastCap and FastHenry, from MIT (Massachusetts Institute of Technology) are two free parasitics extractor tools for capacitance, and inductance and resistance. Quoted in many scientific articles, are considered golden references in their field. Windows versions with viewer and editor are freely available from FastFieldSolvers. [2][3]
Star-RCXT
Star-RCXT from Synopsys (previously from Avanti) is a universal parasitics extractor tool applicable for a full range of electronic designs.[4]
QRC
QRC from Cadence is a parastics extractor tool for both digital and analog designs. [5]
See also
- Standard Parasitic Exchange Format
- Detailed Standard Parasitic Format
References
- ^ "Automatic Layout Modification", by Michael Reinhardt, p. 120
- ^ MIT Computational Prototyping Group
- ^ FastFieldSolvers
- ^ Star-RCXT
- ^ [1]
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