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QorIQ

 
Wikipedia: QorIQ

QorIQ is Freescale's brand of future 32-bit Power Architecture based communications microcontrollers. It is the evolutionary step from the PowerQUICC platform and will be built around one or more Power Architecture e500mc cores and come in five different product platforms, P1, P2, P3, P4 and P5, segmented by performance and functionality. The platform keeps software compatibility with older PowerPC products such as the PowerQUICC platform.

The QorIQ brand and the P1, P2 and P4 product families was announced in June 2008. Details of P3 and P5 products are yet to be announced.

All QorIQ processors will be manufactured on a 45 nm fabrication process and will be available in the end of 2008 (P1 and P2) and mid 2009 (P4). The roadmap stretched beyond the 32 nm process, and all are pushing a very aggressive power envelope target, capping at 30 W.

Contents

Products

All QorIQ processors are based on Power Architecture e500v2 cores. As such each processor core shares a common feature set such as 32/32 kB data/instruction L1 cache, 36-bit physical memory addressing, a double precision floating point unit and support for virtualization through a hypervisor layer. The dual and multi-core devices will be supporting both symmetric and asymmetric multiprocessing, and can run multiple operating systems in parallel.

P1

The P1 series is tailored for gateways, Ethernet switches, wireless LAN access points, and general-purpose control applications. It is the entry level platform, ranging from 400 to 800 MHz devices. It is designed to replace the PowerQUICC II Pro and PowerQUICC III platforms. The chips include among other integrated functionality, Gigabit Ethernet controllers, two USB 2.0 controllers, a security engine, a 32-bit DDR2 and DDR3 memory controller with ECC support, dual four-channel DMA controllers, a SD/MMC host controller and high speed interfaces which can be configured as SerDes lanes, PCIe and SGMII interfaces. The chip is packaged in 689-pin packages which are pin compatible with the P2 family processors.

P2

The P2 series is designed for a wide variety of applications in the networking, telecom, military and industrial markets. It will be available in special high quality parts, with junction tolerances from -40 to 125 °C, especially suited for demanding out doors environments. It is the mid-level platform, with devices ranging from 800 MHz up to 1.2 GHz. It is designed to replace the PowerQUICC II Pro and PowerQUICC III platforms. The chips include, among other integrated functionality, a 512 kB L2 cache, a security engine, three Gigabit Ethernet controllers, a USB 2.0 controller, a 64-bit DDR2 and DDR3 memory controller with ECC support, dual four-channel DMA controllers, a SD/MMC host controller and high speed SerDes lanes which can be configured as three PCIe interfaces, two RapidIO interfaces and two SGMII interfaces. The chips are packaged in 689-pin packages which are pin compatible with the P1 family processors.

P3

The details of QorIQ P3 series are yet to be announced but is designed to ease the transition to a many-core platform utilizing the CoreNet coherency fabric.

P4

The P4 series is a high performance networking platform, designed for backbone networking and enterprise level switching and routing. The P4 family offers an extreme multi-core platform, with support for up to eight Power Architecture e500mc cores at frequencies up to 1.5 GHz on the same chip, connected by the FlexNet coherency fabric. The chips include among other integrated functionality, integrated L3 caches, memory controllers, multiple I/O-devices such as DUART, GPIO and USB 2.0, security and encryption engines, a queue manager scheduling on-chip events and a SerDes based on-chip high speed network configurable as multiple Gigabit Ethernet, 10 Gigabit Ethernet, RapidIO or PCIe interfaces.

The cores are supported by a hardware hypervisor and can be run in symmetric or asymmetric mode meaning that the cores can run and boot operating systems together or separately, restering and partitioning cores and datapaths independently without disturbing other operating systems and applications.

  • P4080 – Includes eight e500 cores, each with 32/32 instruction/data L1 caches and a 128 kB L2 cache. The chip has dual 1 MB L3 caches, each connected to a 64-bit DDR2/DDR3 memory controller. The chip contains a security and encryption module, capable of packet parsing and classification, and acceleration of encryption and regexp pattern matching. The chip can be configured with up to eight Gigabit and two 10 Gigabit Ethernet controllers, three 5 GHz PCIe ports and two RapidIO interfaces. It also has various other peripheral connectivity such as two USB2 controllers. It is designed to operate below 30 W at 1.5 GHz. The processor is manufacured on a 45 nm SOI process and begun sampling to customers in August 2009.[1]

To help software developers and system designers get started with the QorIQ P4080, Freescale worked with Virtutech to create a virtual platform for the P4080 that can be used prior to silicon availability to develop, test, and debug software for the chip. Currently, the simulator is only for the P4080, not the other chips announced in 2008[2].

Because of its complete set of network engines, this processor can be used for telecommunication systems (LTE eNodeB, EPC, WCDMA, BTS), so Freescale and 6WIND ported the 6WIND's Fast Path on the P4080.

P5

The details of QorIQ P5 series are yet to be announced but it is designed to be Freescale's highest performing processing platform.

System Design

Networking, IT and telecommunication systems

The QorIQ products bring some new challenges in order to design some control planes of telecommunication systems and their data plane. For instance, when 4 or 8 cores are used, such as the P4080, in order to achieve millions of Packet Processing per seconds, the system does not scale with regular software stack because so many cores require a different system design. In order to restore simplicity and still get the highest level of performance, the telecommunication systems are based on a segregation of the cores. Some cores are used for the control plane while some others are used for a re-designed data plane based on a Fast Path.

To help software developers to get a ready to run and the fastest data plane on the QorIQ, Freescale worked with 6WIND to create a turnkey data plane and packet engine platform since 2008[3].

See also

References

  1. ^ http://media.freescale.com/phoenix.zhtml?c=196520&p=irol-newsArticle&ID=1324841&highlight=&tid=rsspr
  2. ^ Virtutech page about P4080 simulation support
  3. ^ P4080 Fast Path

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