R8000

The R8000, also known as the TFP (for Tremendous Floating-Point), is a microprocessor chip set implementing the MIPS IV instruction set architecture (ISA) jointly developed by MIPS Technologies, Inc. (MTI), then a subsidiary of Silicon Graphics, Inc. (SGI), Toshiba and Weitek.^[1] It was notable for being the first implementation of the MIPS IV ISA and the first superscalar MIPS microprocessor.

History

Development of the R8000 started in the early 1990s at SGI. The R8000 was specifically designed to provide the performance of circa 1990s supercomputers with a microprocessor instead of a central processing unit (CPU) built from many discrete components such as gate arrays. At the time, the performance of traditional supercomputers was not advancing as rapidly reduced instruction set computer (RISC) microprocessors. It was predicted that RISC microprocessors would eventually match the performance of more expensive and larger supercomputers at a fraction of the cost and size, making computers with this level of performance more accessible and enabling deskside workstations and servers to replace supercomputers in many situations.

First details of the R8000 emerged in April 1992 in an announcement by MIPS Computer Systems detailing future MIPS microprocessors. In March 1992, SGI announced it was acquiring MIPS Computer Systems, and the company became a subsidiary of SGI called MIPS Technologies, Inc. (MTI) in mid-1992. Development of the R8000 was transferred to MTI, where it continued. The R8000 was expected to be introduced in 1993, but it was delayed until mid-1994. The first R8000, a 75 MHz part, was introduced on 7 June 1994. It was priced at US$2,500 at the time. In mid-1995, a 90 MHz part appeared in systems from SGI. The R8000's high cost and narrow market (technical and scientific computing) restricted its market share, and although it was popular in its intended market, it was largely replaced with the cheaper and generally better performing R10000 introduced January 1996.

Users of the R8000 were SGI, who used it in their Power Indigo2 workstation, Power Challenge server, Power ChallengeArray cluster and Power Onyx visualization system. In the November 1994 TOP500 list, 50 systems out of 500 used the R8000. The highest ranked R8000-based systems were four Power Challenges at positions 154 to 157. Each had 18 R8000s.^[2]

Description

The R8000 consisted of two chips, the R8000 microprocessor and the R8010 floating-point unit. These two chips were also accompanied by application-specific integrated circuits (ASICs) which implemented the control hardware for the secondary cache.

R8000

The R8000 contained the majority of the chip set's logic and transistors. It executed integer instructions in integer execution units and contained the integer register file, primary caches and hardware for instruction fetch, branch prediction and translation lookaside buffers (TLBs).

The integer register file consisted of thirty-two 64-bit entries with nine read ports and four write ports. Four read ports are used to supply operands to two of the four execution units, and an additional four are used to supply operands to the two address generators. A single read port is used to deliver data to the two banks of data cache. Two write ports are used to write results from two functional units to the register file, and two write ports are used by the register file to read from the data cache, one for each bank.

Integer functional units consisted of two integer units, a shift unit, a multiply and divide unit, and two address generator units. Multiply and divide instructions are executed in the multiply-divide unit, which is not pipelined. As a result, the latency for a multiply instruction is four cycles for 32-bit operands and six cycles for 64-bit. The latency for a divide instruction depends on the number of significant digits in the result and thus it varies from 21 to 73 cycles.

R8010

The R8010 executed floating-point instructions. The R8010 is decoupled from the integer pipeline, thus implementing a limited form of out-of-order execution. This was done to hide the remaining latency of the secondary cache. It consisted of two execution units, the floating-point register file, a load queue and a store queue. The two execution units were identical, and executed double precision fused multiply-adds, adds, multiplies, divides and floating-point to integer conversions. The execution units are fully pipelined and bypassed. However, hardware for divides and square-roots was not pipelined. As a result, single and double precision divides require 14 and 20 cycles, respectively;^[3] and single and double precision square-roots require 14 and 23 cycles, respectively.^[4]

Cache

The R8000 used a split level cache. Integer data is fetched from a primary cache located on the R8000 die. Floating-point data is from a primary cache located externally. The same external cache also serves as a unified secondary cache for integer instructions and data.

This scheme was used as the R8000 was designed for sustained floating-point performance. The R8010 floating-point unit required large amounts of data and executed a large amount of instructions so if a small high bandwidth primary cache was used, it would be emptied rapidly, prompting the microprocessor to refill the cache with new data. This restricted the floating-point performance so a large external cache with high bandwidth but also a higher latency, was used instead as it could provide the microprocessor with data continuously.

To mitigate some of the latency, the cache was pipelined and has five stages. During the first stage, the R8000 sends addresses to the tag RAM, which are accessed during the second stage. The third stage is for the signals from the tag RAM to propagate to the data SRAMs. Access of the data SRAMs occurs during the forth cycle with data being returned to the R8000 and R8010 during the fifth stage. A cycle was given for signals to propagate as transistor-transistor logic (TTL) drivers operating at 75 MHz with high loading require an entire cycle and because an extra stage avoided restricting the microprocessor from operating at higher clock frequencies in the future.

Primary caches

The data cache has a 16 KB capacity. It is dual-ported, and is accessed via two 64-bit buses. It can service two loads or one load and one store per cycle. The cache is not protected by parity or by error correcting code (ECC). In the event of a cache miss, the data must be loaded from the streaming cache with an eight-cycle penalty. The cache is virtually indexed, physically tagged, direct mapped, has a 32-byte line size and uses a write-through with allocate protocol.

Physical

The R8000 contained 2.6 million transistors and measured 17.34 by 17.30 mm (299.98 mm²). The R8010 contained 830,000 transistors. In total, the chip set contained 3.43 million transistors. Both were fabricated by Toshiba in their VHMOSIII process, a 0.7 µm, triple-layer metal complementary metal–oxide–semiconductor (CMOS) process. Both are packaged in 591-pin ceramic pin grid array (CPGA) packages. The chipset used a 3.3 V power supply and the R8000 dissipated 13 W at 75 MHz.

Notes

References

• Dongarra, Jack J.; Meuer, Hans W. and Strohmaier, Erich (9 November 1994). TOP500 Supercomputer Sites.
• Gwennap, Linley (15 February 1993). "SGI Provides Overview of TFP CPU". Microprocessor Report, Volume 7, Number 2.
• Gwennap, Linley (23 August 1993). "TFP Designed for Tremendous Floating Point". Microprocessor Report, Volume 7, Number 11.
• Hsu, Peter Yan-Tek (2 June 1994). Design of the R8000 Microprocessor.
• MIPS Technologies, Inc. (August 1994). R8000 Microprocessor Chip Set Product Overview.
• Pountain, Dick (September 1994). "The Last Bastion". Byte.

Further reading

• Ikumi, N. et al. (February 1994). "A 300 MIPS, 300 MFLOPS four-issue CMOS superscalar microprocessor". ISSCC Digest of Technical Papers.
• Unekawa, Y. et al. (April 1994). "A 110-MHz/1-Mb synchronous TagRAM". IEEE Journal of Solid-State Circuits 29 (4): pp. 403–410.