Originally a proprietary bus from Sun, the Sbus has been released into the public domain. The IEEE standardized a 64-bit version in 1993.
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Originally a proprietary bus from Sun, the Sbus has been released into the public domain. The IEEE standardized a 64-bit version in 1993.
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| Wikipedia: SBus |
| SBus | |
Four SBus slots |
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| Year created: | 1989 |
| Created by: | Sun Microsystems |
| Superseded by: | PCI (1997) |
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| Width in bits: | 32 |
| Number of devices: | 8 masters, unlimited slaves |
| Capacity | 16.67 MHz - 25 MHz |
| Style: | Parallel |
| Hotplugging? | no |
| External? | no |
SBus is a computer bus system that was used in most SPARC-based computers (including all SPARCstations) from Sun Microsystems and others during the 1990s. It was introduced by Sun in 1989 to be a high-speed bus counterpart to their high-speed SPARC processors, replacing the earlier (and by this time, outdated) VMEbus used in their Motorola 68020- and 68030-based systems and early SPARC boxes. When Sun moved to open the SPARC definition in the early 1990s, SBus was likewise standardized and became IEEE-1496. In 1997 Sun started to migrate away from SBus to PCI, and today SBus is no longer used.
The industry's first 3rd party SBus cards were announced in 1989 by Antares Microsystems. These were:- the 10Base-2 Ethernet Controller, the SCSI-SNS Host Adapter, the Parallel Port, and the 8-Channel Serial Controller.
A technical guide to the bus was published in 1992 in book form. "SBus Information Applications and Experience" was written by James D. Lyle who founded Troubador Technologies.
At the peak of the market over 250 manufacturers were listed in the SBus Product Directory, which was renamed to the SPARC Product Directory in 1996.
SBus is in many ways a "clean" design. It was targeted only to be used with SPARC processors, so most cross-platform issues were not a consideration. SBus is based on a big-endian 32-bit address and data bus, can run at speeds ranging from 16.67 MHz to 25 MHz, and is capable of transferring up to 100 MB/s. Devices are each mapped onto a 28-bit address space (256 MB). Only eight masters are supported, although there can be an unlimited number of slaves.
When the 64-bit UltraSPARC was introduced, SBus was modified to use clock doubling and transfer two 32-bit data words per cycle to produce a 200 MB/s 64-bit bus. This variant of the SBus architecture used the same 96-pin connector as the older one.
SBus cards have a very compact form factor; a single-width card is 3 inches wide by 5 inches long and is designed to be mounted parallel to the motherboard. This allowed for three expansion slots in the slim "pizza box" enclosure of the SPARCstation 1. The design also allows for double- or triple-width cards that take up two or three slots, as well as double-height (two 3x5 inch boards mounted in a "sandwich" configuration) cards.
SBus was a peripheral interconnect only; some Sun systems used MBus, another standardized system, as a CPU-memory bus.
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