A soft microprocessor (also called softcore microprocessor or a soft processor) is a microprocessor core that can be wholly implemented using logic synthesis. It can be implemented via different semiconductor devices containing programmable logic (e.g., ASIC, FPGA, CPLD).
Most systems, if they use a soft processor at all, only use a single soft processor. However, a few designers tile as many soft cores onto an FPGA as will fit[1]. In those multi-core systems, rarely-used resources can be shared between all the cores in a cluster, leading to Jan's Razor.
Jan's Razor: In a chip multiprocessor design, strive to leave out all but the minimal kernel set of features from each processing element, so as to maximize processing elements per die.
[2]—Jan Gray
Core comparison
| Processor |
Developer |
Open Source |
Bus Support |
Notes |
Project Home |
| TSK3000A |
Altium |
No - Royalty Free |
Wishbone |
32-bit R3000 style RISC Modified Harvard Architecture CPU |
Embedded Design on Altium Wiki |
| TSK51/52 |
Altium |
No - Royalty Free |
Wishbone / Intel 8051 |
8-bit Intel 8051 instruction set compatible, lower clock cycle alternative |
Embedded Design on Altium Wiki |
| OpenSPARC T1 |
Sun |
Yes |
|
64-bit |
OpenSPARC.net |
| MicroBlaze |
Xilinx |
No |
PLB, OPB, FSL, LMB |
|
Xilinx MicroBlaze |
| PicoBlaze |
Xilinx |
Yes |
|
|
Xilinx PicoBlaze |
| Nios, Nios II |
Altera |
No |
Avalon |
|
Altera Nios II |
| Cortex-M1 |
ARM |
No |
|
|
[1] |
| eSi-RISC |
EnSilica |
No |
AMBA AXI and APB |
Configurable as 16 or 32-bit. Supports ASIC and FPGA. |
EnSilica eSi-RISC |
| Mico32 |
Lattice |
Yes |
Wishbone |
|
LatticeMico32 |
| LEON 3 |
ESA |
Yes |
AMBA |
SPARC V8 compatible in 25k gates |
Gaisler |
| OpenRISC |
OpenCores |
Yes |
|
32-bit; Done in ASIC, Altera, Xilinx |
OR1K |
| AEMB |
Shawn Tan |
Yes |
Wishbone |
MicroBlaze EDK 3.2 compatible Verilog core |
AEMB |
| OpenFire |
Virginia Tech CCM Lab |
Yes |
OPB, FSL |
Binary compatible with the MicroBlaze |
[2] |
| PacoBlaze |
Pablo Bleyer |
Yes |
|
Compatible with the PicoBlaze processors |
PacoBlaze |
| xr16 |
Jan Gray |
No |
XSOC abstract bus |
16-bit RISC CPU + SoC featured in Circuit Cellar Magazine #116-118 |
XSOC/xr16 |
| ZPU |
Zylin AS |
Yes |
Wishbone |
Stack based CPU, configurable 16/32 bit datapath, eCos support |
Zylin CPU |
See also
References
External links
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