StrongARM

DEC StrongARM SA-110 Microprocessor

The StrongARM is a family of microprocessors that implemented the ARM V4 instruction set architecture (ISA). It was developed by Digital Equipment Corporation (DEC) and later sold to Intel, who continued to manufacture it before replacing it with the XScale.

History

The StrongARM was a collaborative project between DEC and ARM to create a faster microprocessor based on (but not totally compatible with) the existing ARM line. The StrongARM was designed to address the upper-end of the low-power embedded market, where users needed more performance than the ARM could deliver while being able to accept more external support. Targets were devices such as newer personal digital assistants and set-top boxes.^[1]

Traditionally, the semiconductor division of DEC was located in Massachusetts. In order to gain access to the design talent in Silicon Valley, DEC opened a design center in Palo Alto, California. This design center was led by Dan Dobberpuhl and was the main design site for the StrongARM project. Another design site which worked on the project was in Austin, Texas that was created by some ex-DEC designers returning from Apple Computer and Motorola. The project was set up in 1995, and quickly delivered their first design, the SA-110.

This was immediately incorporated into newer versions of the Apple Newton, the Acorn Risc PC, Eidos Optima video editing system, as well as a number of other products.

StrongARM was sold to Intel as part of a lawsuit settlement in 1997.^[2] Intel used the StrongARM to replace their ailing line of RISC processors, the i860 and i960.

A new StrongARM core, the SA-2 was developed by Intel.^[3] It was introduced in 2000 as the XScale.

When the semiconductor division of DEC was sold off to Intel, the Palo Alto design group spun off to become SiByte, a start-up company building MIPS architecture SOCs for the networking market. The Austin design group spun off to become Alchemy Semiconductor, another start-up company building MIPS SOCs for the hand-held market.

Description

The StrongARM family are faster versions of the existing ARM processors with a somewhat different instruction set. Clocked at 206MHz they can perform up to 235 MIPS (1.14 MIPS/MHz). They have limited software compatibility with the earlier ARM families due to their separate caches for data and instructions, which causes self-modifying code to fail. These features were later included in some ARMv4 architectures (notably, the ARM/Texas Instruments ARM925). The StrongARM has an "invalidate cache line" instruction to let the CPU know to reload from main memory. This situation arises rarely in typical software however, and StrongARM is not the only processor to have made such a sacrifice. The Motorola 68020, for instance, caused similar compatibility problems for any software designed for the earlier 68000 and 68010 models^{[citation needed]}.

SA-110

The SA-110 was the first microprocessor in the StrongARM family. It was introduced in early 1996, debuting at 200 MHz. In October 1996, a 233 MHz version was introduced. Throughout 1996, the SA-110 was the highest performing microprocessor for portable devices.^[4] The SA-110 was available in 100, 160, 166, 200, 233 MHz versions. The SA-110's first design win was the Apple MessagePad 2000.^[5] The SA-110's lead designers were Daniel W. Dobberpuhl, Gregory W. Hoeppner, Liam Madden, and Richard T. Witek.

Description

The SA-110 had a simple microarchitecture. It was scalar, in-order design with a five-stage classic RISC pipeline. The microprocessor was partitioned into several blocks, the IBOX, EBOX, IMMU, DMMU, BIU, WB and PLL. The IBOX contained hardware that operated in the first two stages of the pipeline such as the program counter. It fetched, decoded and issued instructions. It also handled branch instructions. The SA-110 did not have branch prediction hardware, but had mechanisms for their speedy processing. Complex ARM instructions were translated by the IBOX into sequences of simpler instructions by during the second stage.

Instructions are executed in the third stage by hardware in the EBOX. The EBOX contained the register file, arithmetic logic unit (ALU), barrel shifter, multiplier and condition code logic. The register file had three read ports and two write ports. The ALU and barrel shifter executed instructions in a single cycle. The multiplier had a latency of multiple cycles.

The IMMU and DMMU are memory management units for instructions and data, respectively. Each MMU contained a 32-entry fully-associative TLB that can map 4 KB, 64 KB or 1 MB pages. The write buffer (WB) has eight 16-byte entries. It enables the pipelining of stores. The bus interface unit (BIU) provided the SA-110 with an external interface.

The PLL generates the internal clock from a 3.68 MHz input clock. It was not designed by DEC, but was contracted to the Centre Suisse d'Electronique et de Microtechnique (CSEM) located in Neuchâtel, Switzerland.

The Icache and Dcache each have a capacity of 16 KB and are 32-way set associative and virtually addressed. The SA-110 was designed with slow (and therefore low cost) memory in mind and therefore the high set associativity allows a higher hit rate than competing designs, and the use of virtual addresses allows memory to be simultaneously cached and uncached. The caches take up half the die area.

The SA-110 contained 2.5 million transistors and measured 7.8 mm by 6.4 mm for an area of 49.92 mm². It was fabricated by DEC in their CMOS-6 process, their sixth-generation complementary metal–oxide–semiconductor (CMOS) process with some modifications. CMOS-6 has a 0.35 µm feature size, a 0.25 µm effective channel length but for use with the SA-110, only three levels of aluminium interconnect. It used a power supply with a variable voltage of 1.2 to 2.2 V to enable designs to find a balance between power consumption and performance (higher voltages enable higher clock rates).

SA-1100

The SA-1100 was a derivative of the SA-110 developed by DEC initially targeted for PDAs. It has an integrated color LCD controller. The SA-1100 had a companion chip, the SA-1101. The companion chip provided additional peripherals to complement those integrated on the SA-1100 such as a video output port, two PS/2 ports, a USB controller and a PCMCIA controller that replaces that on the SA-1100. It was developed by DEC, but was only partially complete when StrongARM was acquired by Intel, who had to finish the design. It was fabricated at DEC's former Hudson, Massachusetts fabrication plant, which was also sold to Intel.^[6]

It contained 2.5 million transistors and measured 8.24 mm by 9.12 mm (75.15 mm²). It was fabricated in a 0.35 µm CMOS process with three levels of aluminium interconnect and was packaged in a 208-lead thin quad flat pack (TQFP).^[7]

SA-1110

The SA-1110 was a derivative of the SA-110 developed by Intel introduced in 1999. It operated at 133 or 206 MHz and added an on-die memory controller that supports 66 (133 MHz version only) or 103 MHz (203 MHz version only) SDRAM.^[8] It was used in mobile phones, personal data assistants (PDAs) such as the Compaq (later HP) iPAQ and HP Jornada, and the Simputer.^[9]

SA-1500

The SA-1500 was a derivative of the SA-110 developed by DEC initially targeted for set top boxes.^[10][11] It was designed and manufactured in low volumes by DEC but was never put into production by Intel. The SA-1500 operated at 200 to 300 MHz. New features include a floating-point unit and SIMD instructions. A companion chip provided additional video and audio processing capabilities.

It contains 3.3 million transistors and measures 60 mm². It was fabricated in a 0.28 µm CMOS process. It used a 1.5 to 2.0 V internal power supply and 3.3 V I/O, consuming less than 0.5 W at 100 MHz and 2.5 W at 300 MHz. It was packaged in a 240-pin metric quad flat package (MQFP) or a 256-ball ball grid array.

References

Further reading

• Halfhill, Tom R. (19 April 1999). "Intel Flexes StrongARM With New Chips". Microprocessor Report.
• Santhanam, S. et al. (1998). "A low-cost, 300-MHz, RISC CPU with attached media processor". IEEE Journal of Solid-State Circuits, Volume 33, Issue 11.
• Turley, Jim (13 November 1995). "StrongArm Punches Up ARM Performance". Microprocessor Report.
• Turley, Jim (15 September 1997). "SA-1100 Puts PDA on a Chip". Microprocessor Report.
• Witek, Rich; Montanaro, James (1996). "StrongARM: A high-performance ARM processor". Proceedings of COMPCON '96, pp. 188–191.