Transmission gate

CMOS Transmission Gate

A transmission gate is an electronic element. It is a good non-mechanical relay, built with CMOS technology. Sometimes known as an analog gate, analogue switch or electronic relay depending on its use. It is made by the parallel combination of an nMOS and a pMOS transistor with the input at the gate of one transistor being complementary to the input at the gate of the other.

Operation

A current can flow through this element in either direction. Depending on whether or not there is a voltage on the gate, the connection between the input and output is either low-resistance or high-resistance, respectively. R_on = 100 ohm and R_off > 5 megohm. This can effectively isolate the output from the input. See the truth table at the right to represent this logic.

The operation can also be understood this way: when the gate input to the nMOS transistor is '0',and the complementary '1' is gate input to the pMOS, both are turned off. However when gate input to the nMOS is '1' and its complementary '0' is the gate input to the pMOS, both are turned on and passes any signal '1' or '0' equally well without degradation. The use of transmission gates eliminates the undesirable threshold voltage effects which give rise to loss of logic levels in pass-transistors.

The above logic was invented as a solution to problems of earlier CMOS logics. It enables certain logic functions to be implemented with fewer transistors than possible using other CMOS logic.

This logic can be used to design multiplexers.

Design

It would seem that a transmission gate could be constructed using simply a single pMOS or nMOS transistor. If only an individual nMOS transistor were to be used, and there was a high voltage out the OUT and a low voltage on the IN and we are trying to transmit the zero to the OUT, then the nMOS will drain some of the voltage but not all of it leaving the OUT somewhere in the "no man's land" voltage region of digital circuits. Adding the pMOS gate in parallel allows all the voltage to drain after the nMOS shuts off before all the voltage is drained. This also solves the problem when transmitting a high voltage to OUT.¹

See also

• Tri-state logic

Sources

• What is a Transmission Gate (Analog Switch)?
• http://www.nanohub.org/courses/nanoscale_transistors - Mark Lundstrom (Lecture 24)