Bus cycle - clock cycles taken to complete one bus transaction. Instruction cycle - clock cycles taken to complete execution of one instruction
The address bus is a section of the bus that emits the address of the desired instruction or operand.
The lock prefix on the 8086/8088 prevents any other bus master from accessing the bus during this instruction, even if this instruction is a multiple access instruction. It assures atomicity and data consistency in a multi-computer environment, but only for a single instruction. It is generally used to manipulate a mutex or semaphore.
Lets put this one into a very tangible form. 8-Bit Bus: To process the text string "ABBA" an 8 bit bus will send the data like this(I'm using ABBA because its a band name and its very easy to write in binary): Instruction #1 [01000001] Instruction #2 [01000010] Instruction #3 [01000010] Instruction #4 [01000001] A 32-bit bus does lit like this: Instruction #1 [01000001];[01000010];[01000010];[01000001] At the most elemental scale, this would make a 32-bit bus 4 times faster than a 8-bit bus at the same frequency. More goes into it than this, however, and real-world numbers are never an exact representation of theoretical performance differences.
The Instruction Pointer (IP) in an 8086 microprocessor contains the address of the next instruction to be executed. The processor uses IP to request memory data from the Bus Interface Unit, and then increments it by the size of the instruction.
The bus interface unit provides the func- tions related to instruction fetching and queuing, op- erand fetch and store, and address relocation. This unit also provides the basic bus control. The overlap of instruction pre-fetching provided by this unit serves to increase processor performance through improved bus bandwidth utilization. Up to 6 bytes of the instruction stream can be queued while waiting for decoding and execution.
program counter holds the address of the next instruction.
Instruction register:- it hold's the instruction decoded bu control unit.. if you know that bus is the communication Chanel of computer system, whenever we enter some instruction it's going to pass by bus. but we send instruction in human understandable form so all data should be convert in bus understandable form. now all data convert in bus understandable form but here is the problem that what C.P.U. not able to understand that , so control unit convert all instruction in c.p.u. understandable form now all data converted in c.p.u. understandable form but still there in c.p.u. going some process so it can accept that thing right now ..so it can store in some where in c.p.u. that called instruction register.. I.R is the one type of register.it can hold very small amount of data.
There are 2 kinds Data bus and address bus data bus which carries the data ( includes both instruction and data). address bus which carries where the data in the data bus must be sent to in the RAM or which I/O device has to be active to read / write data to the data bus .
The execution unit execute the instruction while the bus interface unit do the fetching and shows the results as an output
8086 has two blocks Bus Interfacing Unit(BIU) and Execution Unit(EU).The BIU performs all bus operations such as instruction fetching, reading and writing operands for memory and calculating the addresses of the memory operands. The instruction bytes are transferred to the instruction queue.EU executes instructions from the instruction system byte queue.Both units operate asynchronously to give the 8086 an overlapping instruction fetch and execution mechanism which is called as Pipelining. This results in efficient use of the system bus and system performance.BIU contains Instruction queue, Segment registers, Instruction pointer, Address adder.EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register,Flag register.
Responsible for: o Performing all external bus operations (timing, interfacing) and: § Instruction fetch § Reading/writing data operands from/to memory § Inputting/outputting data for I/O peripherals § These information transfers take place over the system bus o Performing instruction queuing, and phyis-address generation