If this is a homework assignment, you really should consider doing it yourself
The MVI instruction in the 8085 microprocessor contains 7 or 10 T-Cycles, each one clock cycle, not including wait states. Each cycle starts on the falling edge of CLK.
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T1a - ALE goes high for one half clock. During this time, S0, S1, IO/M-, A15-A8, and AD7-AD0 become valid, and are guaranteed valid at the falling edge of ALE. (AD7-AD0 represent A7-A0, and must be strobed by external hardware.) A15-A0 will be the address of the MVI instruction. Somewhat after ALE, AD7-AD0 will float.
T2a - RD- goes low for one clock cycle. While RD- is low, the external hardware has permission to drive AD7-AD0. It must supply the opcode for MVI. READY is sampled at the beginning of T2 - If it is low, T2 will be repeated, until READY is sampled high.
T3a - RD- remains low for one more half clock cycle. The external hardware must guarantee AD7-AD0 valid by the beginning of T3a. The 8085 samples AD7-AD0 at the beginning of T3a. This will give it the MVI opcode.
T4a - Nothing happens externally. All lines persist their prior state. The 8085 processes the MVI opcode and sets itself up for the required actions.
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T1b - This is the same timing as T1a, except that the address is one greater.
T2b - This is the same timing as T2a. During this time, the external hardware must drive the immediate value of the MVI instruction onto AD7-AD0.
T3b - This is the same timing as T3a. At the conclusion of T3b the 8085 knows the value to store in the destination. If the destination was an internal register, the instruction is complete. If the destination was M, the cycles continue.
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T1c - This is the same timing as T1a, except that the address is the contents of the HL register, H sent on A15-A8, and L sent on AD7-AD0.
T2c - This is the same timing as T1a, except that WR- is used instead of RD-, and the AD7-AD0 lines do not float - they emit the immediate value retrieved in T3b. The AD7-AD0 line will change sometime between ALE and WR-.
T3c - This is the same timing as T3a, except that WR- goes high at the beginning instead of at the halfway point. The external hardware is expected to save the AD7-AD0 lines into the address specified during T1c on the rising edge of WR-. The 8085 will persist the AD7-AD0 lines for one half clock cycle to guarantee the AD7-AD0 lines.
So now
6 T state Opcode fetch
+ Memory write * 2 (PC pushed to stack) ( 3+3 )
+ Memory read * 2 (New value of PC fetched from memory) ( 3+3 )
ie 6 + 3 + 3 + 3 + 3 = 18 T-states.
" It is so simple to be happy,
it has 5 machine cycles,
1)opcode fetch-after decoding the meaning of this opcode,
2)MEMORY READ--the content of memory location shown by stack pointer(sp) is transferred to up,sp->sp+1 .
3)MEMORY READ-- the content of memory location shown by stack pointer(sp) is transferred to up.
4)MEM WRITE--content of H reg goes to sp & sp->sp-1.
5)MEM WRITE--content of L reg goes to sp.
[by Vishal Barun]
Refer http://wiki.answers.com/Q/How_to_draw_timing_diagram_for_8085_microprocessor_instruction
3 machine cycles...
1.Opcode fetch
2.read cycle
3.read cycle
It will consists of a FETCH cycle followed by 1 or more wait cycles. Once HLT is executed it inserts wait states in every clock period until it is retested or an interrupt occurs.
sorry
loop: mvi c,59 dcr c mov a,c daa movc,a jnz loop end
4000 lda 50003a,00,504003 mvi b 0206,024005 mov c,a4f4006 mov d,a574007loop2mvi a 003e,004009loop1add d82400a dcr c0d400b jnz loop1c2,09,40400e mov c,a4f400f dcr b054010 jnz loop2c2,07,404013 mov a,c794014 sta 500532,05,504017 hlt76 enjoy dear friends :) by abin james nellanikattu
Lxih, 2200 mov c,m inxh mov a,m inxh cmp m jc l1 mov a,m dcr c jnz l2 inhx mov m,a hlt
JNC is Jump No-Carry, so the carry flag is checked. JNZ is Jump No-Zero, so the zero flag is checked.
Block transfer in 8085... PUSH FLAGS {optional, if registers need to be saved} PUSH B PUSH D PUSH H LXI H,COUNT LXI B,SOURCE LXI D,DESTINATION LOOP LDAX B STAX D INX B INX D DCX H MOV A,H ORA L JNZ LOOP POP H {optional, if registers need to be saved} POP D POP B POP FLAGS
The airport code for Jinzhou Xiaolingzi Airport is JNZ.
Actually, you don't need JNZ. You simply subtract the low order halves, and then you subtract with borrow the high order halves. You can carry this to any arbitrary precision.
A loop in a microprocessor, like any loop in any programming language, is a series of instructions that is executed repeatedly until some condition is satisfied. An example of a delay loop in the 8085 might be... . PUSH FLAGS . XRA A L INR A . JNZ L . POP FLAGS This piece of code, with a 1 MHz clock, will take about 4.6 mS to execute, and it will save and restore the accumulator and flags.
Xra a [(making the accumulator zero) or you can also write mvi a,00 but will probably take more t-states] lxi h dooo(can be any other address)give the range(n) mov b,m mvi c,01 again: add c inr c dcr b jnz again [loop] inx h mov m,a hlt
Lxi b, 0000h lhld 8000h xchg lhld 8002h dcx d l006: lda 8002h add l mov l, a lda 8003h adc h mov h, a jnc l013 l013: inx b dcx d mov a, d ora e jnz l006 shld 8006h mov l, c mov h, b shld 8004h hlt
its in mnemonics : get the hex code from internet. MVI B,10H(REGISTER B AS A COUNTER) LXI H,C000H(SOURCE REGISTER, H-L AS MEMORY POINTER) LXI D,C050H(DESTINATION REGISTER) L1: MOV A,M STAX D INX H INX D DCR B JNZ L1 RST 1
A possible program to reverse a block of memory using the 8085... PUSH F SAVE PROCESSOR STATE - OPTIONAL PUSH B PUSH D PUSH H LXI H,{address of block} MOV D,H SAVE BLOCK ADDRESS MOV E,H MVI A,{size of block} MOV C,A SAVE BLOCK SIZE LOOP1: MOV A,M GET DATA BYTE PUSH F PUSH ON STACK DCR C DECREMENT LOOP COUNT XRA A TEST FOR END OF LOOP CMP C JNZ LOOP1 MOV H,D RESTORE BLOCK ADDRESS MOV L,E MOVE C,B RESTORE BLOCK SIZE LOOP2: POP F POP FROM STACK MOV M,A PUT DATA BYTE DCR C DECREMENT LOOP COUNT XRA A TEST FOR END OF LOOP CMP C JNZ LOOP2 POP H RESTORE PROCESSOR STATE - OPTIONAL POP D POP B POP F