Because that's how Intel designed the 8085.

In addition to the 8080 type interrupt on the INTR pin, Intel chose, for the 8085, to implement four new interrupts, RST 5.5, RST 6.5, RST 7.5, and TRAP, each of which would not require the interrupting device to provide a vector. The naming convention of x.5 was simply in recognition that Intel placed the implicit vector halfway between two other RST vectors. As an example, RST 6.5 is halfway between RST 6 and RST 7. Since RST 6 and RST 5 are eight bytes away from each other, placing RST 6.5 in between would place a limit of four bytes, and four bytes is enough to place a three byte JMP instruction.

The decimal and hex addresses of all of the vectors are...

RST 0 - 0 - 00H

RST 1 - 8 - 08H

RST 2 - 16 - 10H

RST 3 - 24 - 18H

RST 4 - 32 - 20H

TRAP - 36 - 24H

RST 5 - 40 - 28H

RST 5.5 - 44 - 2CH

RST 6 - 48 - 30H

RST 6.5 - 52 - 34H

RST 7 - 56 - 38H

RST 7.5 - 60 - 3CH

The 5.5 in RST 5.5 means that the interrupt vector is located between RST 5 and RST 6.

RST OF TRAP is 24h(hexadecimail) address.

Because this mnemonic stands for RESTART (RST).

It is angle RST.