Because that's how Intel designed the 8085.
In addition to the 8080 type interrupt on the INTR pin, Intel chose, for the 8085, to implement four new interrupts, RST 5.5, RST 6.5, RST 7.5, and TRAP, each of which would not require the interrupting device to provide a vector. The naming convention of x.5 was simply in recognition that Intel placed the implicit vector halfway between two other RST vectors. As an example, RST 6.5 is halfway between RST 6 and RST 7. Since RST 6 and RST 5 are eight bytes away from each other, placing RST 6.5 in between would place a limit of four bytes, and four bytes is enough to place a three byte JMP instruction.
The decimal and hex addresses of all of the vectors are...
RST 0 - 0 - 00H
RST 1 - 8 - 08H
RST 2 - 16 - 10H
RST 3 - 24 - 18H
RST 4 - 32 - 20H
TRAP - 36 - 24H
RST 5 - 40 - 28H
RST 5.5 - 44 - 2CH
RST 6 - 48 - 30H
RST 6.5 - 52 - 34H
RST 7 - 56 - 38H
RST 7.5 - 60 - 3CH
RST OF TRAP is 24h(hexadecimail) address.
In the 8085, TRAP vectors at 0024H.
The 5.5 in RST 5.5 means that the interrupt vector is located between RST 5 and RST 6.
RST is simply the opcode chosen to represent the Restart instruction.
The lowest priority interrupt in the 8085 microprocessor is INTR, unless you also consider the software interrupts, RST 0 through RST 7, which are even lower.
RIM, SIM, RST, to name three.
The name, RST6.5, was chosen because the interrupt vector lies halfway between RST 6 and RST 7, specifically at address 0034H.
RST 5 is used in place of HLT in the Intel 8085 kit in order to return control to the monitor program. If HLT were used, the processor would stop and so would the monitor.
RST 5.5 is level triggered interrupt & maskable also. it can be masked by using SIM intrruction. Vector address of the RST 5.5 interrupt is 002Ch
RST 5.5 is an interrupt request pin (pin 9) on the 8085. It is sampled, along with other interrupt requests, one clock cycle before ALE on the falling edge of CLK. When enabled, and having priority, it causes an interrupt vector sequence using the RST 5.5 instruction, going to location 002CH.
RSTn(0-7) is software interrupt & RST(7.5,6.5,5.5) are INTEL's 8085 maskable interrupts their priority is respectively 7.5,6.5,5.5.RSTn.5 is hardware intterrupt and it is controlled by the external pin available on the chip of 8085. it is used to interrupt the microprocessor from its normal execution and tends to execute some ISR(interrupt service routine)
The 8085 has five interrupts, INTR, RST5.5, RST6.5, RST7.5, and TRAP. It also has eight software interrupts, RST0, RST1, ..., RST7. The INTR interrupt requires a hardware response that is an opcode. Usually, the opcode is either a CALL instruction, in which case the interrupt vector can go anywhere in memory, or it is an RST instruction, in which case the vector is based on a table in low memory. In the case of RST instructions, either directly or via INTR, or the RSTx.5 interrupts, you simply multiply the interrupt number by 8 to get the vector address. The following table presents the vector addresses for all possible interrupts... RST 0 - 00H RST 1 - 08H RST 2 - 10H RST 3 - 18H RST 4 - 20H TRAP - 24H RST 5 - 28H RST5.5 - 2CH RST 6 - 30H RST 6.5 - 34H RST 7 - 38H RST 7.5 - 3CH