The P6 microarchitecture is the sixth generation Intel x86 microarchitecture, implemented by the Pentium Pro microprocessor that was introduced in November 1995. It is sometimes referred to as i686. It was succeeded by the NetBurst microarchitecture in 2000, but eventually revived in the Pentium M line of microprocessors. The successor to the Pentium M variant of the P6 microarchitecture is the Intel Core microarchitecture.
From Pentium Pro to Pentium III
The P6 core was the sixth generation Intel microprocessor in the x86 space. The first implementation of the P6 core was the Pentium Pro CPU in 1995, the immediate successor to the original Pentium design (P5).
Some techniques first used in the x86 space in the P6 core include:
- Speculative execution and out-of-order completion (called "dynamic execution" by Intel), which required new retire units in the execution core. This lessened pipeline stalls, and in part enabled greater speed-scaling of the Pentium Pro and successive generations of CPUs.
- Superpipelining, which increased from Pentium's 5-stage pipeline to 14 of the Pentium Pro, and eventually morphed into the 10-stage pipeline of the Pentium III, and the 12- to 14-stage pipeline of the Pentium M.
- PAE and wider 36-bit address bus to support 64 GB of physical memory (the linear address space of a process was still limited to 4 GB).
- Register renaming, which enabled more efficient execution of multiple instructions in the pipeline.
- CMOV instructions heavily used in compiler optimization in Linux kernel, glibc and other packages breaking backward compatibility with older IA-32 CPUs (Pentium and Pentium MMX)
The P6 architecture lasted three generations from the Pentium Pro to Pentium III, and was widely known for low power consumption, excellent integer performance, and relatively high instructions per cycle (IPC). When the new NetBurst (P68) architecture was conceived, initially in the Willamette core, which had relatively low IPC and less efficient overall design both in terms of power consumption and throughput efficiency, the P6 line of processing cores were largely thought to be abandoned.
Revived microarchitecture in Pentium M (Banias and Dothan)
Upon release of the Pentium 4-M and Mobile Pentium 4, it was quickly realized that the new mobile NetBurst processors were not ideal for mobile computing. The Netburst-based processors were simply not as efficient per clock or per watt compared to their P6 predecessors. Mobile Pentium 4 processors ran much hotter than Pentium III-M processors and didn't offer significant performance advantages. Its inefficiency affected not only the cooling system complexity, but also the all-important battery life.
Intel, realizing that their new microarchitecture wasn't the best choice for the mobile space, went back to the drawing boards for a design that would be optimally suited for this market segment. The result was a hybrid, and at the time, modernized P6 design called the Pentium M:
Design Overview[1]
- Quad-pumped Front Side Bus. With the initial Banias core, Intel adopted the 400 MHz FSB first used in the Pentium 4. The Dothan core moved to the 533 MHz FSB, following the Pentium 4's evolution.
- Larger L2 cache. Initially 1 MB in the Banias core, then 2 MB in the Dothan core. Dynamic cache activation by quadrant selector from sleep states.
- SSE2 support.
- A 12-14-stage instruction pipeline to achieve higher clock speeds than the Pentium III-M.
- Dedicated register stack management.
- Addition of global history to branch prediction table.
- Micro-ops Fusion of certain sub-instructions mediated by decoding units. x86 commands can be combined into fewer RISC micro operations.
The Pentium M was the most power efficient processor for notebooks for several years, consuming a maximum of 27 watts at maximum load and 4-5 watts while idle. The processing efficiency gains brought about by its modernization allowed it to rival the Mobile Pentium 4 clocked over 1 GHz higher (the fastest-clocked Mobile Pentium 4 compared to the fastest-clocked Pentium M) and equipped with much more memory and bus bandwidth.[1]
Pentium M's primary shortcoming was in the floating point realm. The P6 core had reasonable floating point performance throughout much of its lifetime, but the newer AMD Athlon and Athlon 64 cores, along with the powerful floating point SIMD capabilities of NetBurst processors, outclassed it. Although Intel implemented SSE2 in Pentium M, the implementation was not equal to that within the Athlon 64 or Pentium 4. So, on tasks where Pentium M was relying heavily on its floating point unit instead of its cache and integer performance, it would present disappointing performance.[1][2]
Intel Core (Yonah)
Intel Core processors use a descendant of the P6 microarchitecture called the Core microarchitecture, which was not based as heavily on P6 as the Pentium M was. The Yonah CPU was launched in January 2006 under the Core brand. Single and dual-core versions were sold under the Core Solo and Core Duo brands respectively (the Core Solo processor being a Core Duo, but with one disabled core). These processors provided partial solutions to some of the foregoing Pentium M's shortcomings, by adding to its P6 microarchitecture:
- SSE3 Support
- Single- and Dual-core technology with 2 MB of shared L2 cache (restructuring processor organization)
- Increased FSB speed, with the FSB running at 533 MHz or 667 MHz.
- A 12-stage instruction pipeline.
This resulted in the interim microarchitecture for mobile only CPUs, part way between P6 and the next all processor Core microarchitecture introduced with the CPUs branded Core 2, Pentium Dual-Core, Celeron, and Xeon.
It is important to note, that some Pentium Dual-Core branded CPUs (T2060, T2080 and T2130) are Yonah-based.
Intel Core 2
Main article:
Intel Core 2First launched on July 27, 2006, the Intel Core 2 microprocessors are based on the Intel Core microarchitecture, a distant relative of P6. Dual-core models were branded Core 2 Duo and single core models were branded Core 2 Solo. A quad-core version was added on January 7, 2007, branded Core 2 Quad, and an enthusiast variant on November 14, 2006, branded Core 2 Extreme. Core 2 Quad uses a multi chip module (MCM) design (2 cores per die) while the Core 2 Duo uses a monolithic design (all cores are on one die). The Core 2 Solo is a Core 2 Duo with one core disabled, and does not have a desktop variant. The Core 2 brand will be Intel's final mainstream processor line to use FSB, with all future Intel processors based on the Nehalem microarchitecture and future Intel microarchitectures exclusively using the QPI or DMI bus. Improvements from the Intel Core processors were:
- A 21-stage instruction pipeline to achieve significantly higher clock speeds than the Core processsors.
- SSSE3 support for all models and SSE4.1 support for all Core 2 models manufactured at a 45 nm lithiography.
- A x86-64 (64-bit) instruction set is added, allowing all Core 2 processors run 64-bit applications.
- Increased FSB speed, with the FSB running from 533 MHz to 1600 MHz.
- Increased L2 cache size, with the L2 cache size ranging from 1 MB to 12 MB (Core 2 Duo processors use a shared L2 cache with Core 2 Quad processors having half of the total cache allocated to each die).
- Some mobile Core 2 Duo processors support Dynamic Front Side Bus Throttling, with the FSB running at half of its full speed in Super Low Frequency Mode, therefore reducing the core speed to half of its full speed as well. This technique allows the processors to consume less power, increasing battery life.
- Some mobile Core 2 Duo processors in the have Dynamic Acceleration Technology and mobile Core 2 Quad processors support Dual Dynamic Acceleration Technology. For a mobile Core 2 Duo, this feature allows the CPU to overclock one processor core while turning off the other one. As for a mobile Core 2 Quad, two cores can be overclocked. The processor does this if an application only uses a single core or two as a minimum requirement to function effectively and the clock multiplier is only increased by 1.
P6 based chips
Banias/Dothan variant
Yonah variant
While all these chips are technically derivatives of the Pentium Pro the architecture has gone through several radical changes since its inception.[3]
See also
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P5 based cores |
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0.90 μm
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P6
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P6 based cores |
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Core microarchitecture based cores |
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