Memory interleaving is a method to increase the speed of the high end microprocessors and it is even applicable to the hard disks too. It can be of 2 types: 2 way interleaving(using 2 complete address buses) & 4 way interleaving(using complete 4 address buses). There is a controller too that generates the addresses. CPU can access alternate sections of memory..while one section is busy processing upon a word at a particular location, the other section accesses the word at the next location....resembling overlapping!!!

In a non-interleaved memory system, all of the first bank of memory, bank 0, is addressed before the first long word of the second bank of memory, bank 1, all of bank 1 is addressed before the first long word of bank 2, and so on. Figure 1 shows this organization for two banks of N long words. (A long word is 4 bytes, or 32 bits, and is the natural unit of memory for the 68040.)

Bank 0 Bank 1 ----------------- ----------------- | 0 | | N | ----------------- ----------------- | 1 | | N+1 | ----------------- ----------------- | 2 | | N+2 | ----------------- ----------------- ~ ~ ~ ~ ----------------- ----------------- | N-2 | | 2N-2 | ----------------- ----------------- | N-1 | | 2N-1 | ----------------- ----------------- ^ ^ | | ---------------------------- | v ----------------- | Buffer | ----------------- ^ | v System Data Bus -----------------------------------------------------

Figure 1. Non-interleaved Memory Organization

The 68040 performs burst accesses (a single bus transaction that reads or writes 16 bytes in 4 adjacent long words) to move data between its caches and memory. All 16 bytes come from one bank of DRAM in a non-interleaved memory system, so the time required to complete the transfer depends directly on the access time of the DRAM. Figure 2 shows an example of such a burst access. The time needed to access the 2nd, 3rd, and 4th long words is shorter because a feature of the DRAMs called "page-mode access" is used.

__ __ __ __ __ __ __ __ __ __

Clock __| |__| |__| |__| |__| |__| |__| |__| |__| |__|

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Figure 2. Non-interleaved Burst Access Timing

Interleaved Memory System

In an interleaved memory system, there are still two physical banks of DRAM, but logically the system sees one bank of memory that is twice as large. In the interleaved bank, the first long word of bank 0 is followed by the first long word of bank 1, which is followed by the second long word of bank 0, which is followed by the second long word of bank 1, and so on. Figure 3 shows this organization for two physical banks of N long words. All even long words of the logical bank are located in physical bank 0 and all odd long words are located in physical bank 1.

Bank 0 Bank 1 ----------------- ----------------- | 0 | | 1 | ----------------- ----------------- | 2 | | 3 | ----------------- ----------------- | 4 | | 5 | ----------------- ----------------- ~ ~ ~ ~ ----------------- ----------------- | 2N-4 | | 2N-3 | ----------------- ----------------- | 2N-2 | | 2N-1 | ----------------- ----------------- ^ ^ | | v v ----------------- ----------------- | Buffer | | Buffer | ----------------- ----------------- ^ ^ | | v System Data Bus v -----------------------------------------------------

Figure 3. Interleaved Memory Organization

The interleaved memory configuration is designed to speed up 68040 burst accesses by as much as 30%. (The actual improvement depends on the system clock speed and the DRAM access time.) Since the four long words of a burst access are spread across two physical banks of DRAM, the individual accesses can be overlapped to hide part, or all, of the DRAM access time delay, as shown below in Figure 4.

__ __ __ __ __ __ __ __ __ __ Clock __| |__| |__| |__| |__| |__| |__| |__| |__| |__|

_______________________________ | 1st long word | 3rd lwd | ------------------------------- DRAM Accesses ______________________________ | 2nd long word | 4th lwd | -------------------------------

Figure 4. Interleaved Burst Access Timing

That's it!!!

Non-interleaved Memory System

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