cmos logic circuit uses particularly pmos or nmos viz. passes strong 1 and strong zero respectively and also degraded zero's and one's in their respective cases of p and nmos

so to remove deggraded output the nmos and pmos are combined together for strong output level

NMOS PLA is a Programmable Logic Array which is designed by employing NMOS technology i.e. by employing nmos transistors to realize the required gates of PLA.

PLA is a combination AND gates and OR gates to produced sum of products terms needed for realizing the required combinational logic. It consists of an array of AND gates followed by OR plane. the connections to the AND and OR inputs can be programmed based on our needs.

CMOS and NMOS are two logic families. As the name itself indicates, CMOS is complementary Metal Oxide Semiconductor technology. It uses both PMOS and NMOS transistors for design. Whereas, NMOS logic family uses only NMOS FETs for design.

AOI logic stands for AND OR INVERT logic. AND gate in this logic is formed by two PMOS and two NMOS FETs. Its function is to AND two bits.