PROM

D23128C PROM on the board of ZX Spectrum

A programmable read-only memory (PROM) or field programmable read-only memory (FPROM) or one-time programmable non-volatile memory (OTP NVM) is a form of digital memory where the setting of each bit is locked by a fuse or antifuse. Such PROMs are used to store programs permanently. The key difference from a strict ROM is that the programming is applied after the device is constructed.

These types of memories are frequently seen in video game consoles, mobile phones, radio-frequency identification (RFID) tags, implantable medical devices, high-definition multimedia interfaces (HDMI) and in many other consumer and automotive electronics products.

History

The PROM was invented in 1956 by Wen Tsing Chow, working for the Arma Division of the American Bosch Arma Corporation in Garden City, New York. The invention was conceived at the request of the United States Air Force to come up with a more flexible and secure way of storing the targeting constants in the Atlas E/F ICBM's airborne digital computer. The patent and associated technology was held under secrecy order for several years while the Atlas E/F was the main operational missile of the United States ICBM force. The term "burn," referring to the process of programming a PROM, is also in the original patent, as one of the original implementations was to literally burn the internal whiskers of diodes with a current overload to produce a circuit discontinuity. The first PROM programming machines were also developed by Arma engineers under Mr. Chow's direction and were located in Arma's Garden City lab and Air Force Strategic Air Command (SAC) headquarters.

Commercially available semiconductor antifuse-based OTP memory arrays have been around at least since 1969, with initial antifuse bit cells dependent on blowing a capacitor between crossing conductive lines. Texas Instruments developed a MOS gate-oxide breakdown antifuse in 1979.^[1] A dual-gate-oxide two-transistor (2T) MOS antifuse was introduced in 1982.^[2] Early oxide breakdown technologies exhibited a variety of scaling, programming, size and manufacturing problems that prevented volume production of memory devices based on these technologies. A new antifuse bit cell – a Split Channel device – was introduced by Sidense in November of 2005^[3]. This Split Channel bit cell combines the thick (IO) and thin (gate) oxide devices into one transistor (1T) with a common polysilicon gate.

Programming

A typical PROM comes with all bits reading as 1. Burning a fuse bit during programming causes the bit to read as 0. The memory can be programmed just once after manufacturing by "blowing" the fuses, which is an irreversible process. Blowing a fuse opens a connection while programming an antifuse closes a connection (hence the name).

The bit cell is programmed by applying a high-voltage pulses not encountered during normal operation across the gate and substrate of the thin oxide transistor (around 6V for a 2nm thick oxide, or 30MV/cm) to break down the oxide between gate and substrate. The positive voltage on the transistor’s gate forms an inversion channel in the substrate below the gate, causing a tunneling current to flow through the oxide. The current produces additional traps in the oxide, increasing the current through the oxide and ultimately melting the oxide and forming a conductive channel from gate to substrate. The current required to form the conductive channel is around 100µA/100nm2 and the breakdown occurs in approximately 100µs or less ^[4].

Advantages and Disadvantages

Traditional types of embedded NVM include Flash, mask ROM and eFuse. While ROM and eFuse are one-time-programmable (OTP), Flash memory can be written, erased and rewritten many times and is an example of multi-time programmable NVM. Each of these memories, along with antifuse-based OTP, has both desirable and undesirable characteristics for different types of system applications.

An inherent problem with a 2T MOS antifuse bit cell is predicting where the conductive programming channel will be located. There are three potential regions in which the oxide will break down: above the transistor channel (Region 1 on the diagram), to a leakage control implantation (Region 2) or to the LDD diffusion (Region 3). The bit cell read and programming characteristics are very different for the three regions, which compromises the reliability, yield and portability between processing facilities of arrays using the two-transistor antifuse bit cell.

2T/1.5T Bit cell used in a PROM showing three potential breakpoints or programming areas

The Split Channel (1T) MOS antifuse bit cell eliminates the diffusion area from the thin oxide transistor, ensuring programming is always in the normal transistor channel region. This results in more consistent programming and read characteristics.

The Sidense 1T Split Channel Bit cell used in a PROM showing a single breakpoint or programming area

Notes

References

• View the US "Switch Matrix" Patent #3028659 at US Patent Office or Google
• View the US "Split Channel Antifuse Array Architecture" Patent #7402855 at US Patent Office or Google
• View the US "Method of Manufacturing Semiconductor Integrated Circuits" Patent #3634929 at US Patent Office or Google
• CHOI et al. (2008). "New Non-Volatile Memory Sturctures for FPGA Architectures"