There is not any fullform of verilog.Infact the whole word is called "Verilog HDL" which is "Verilog Hardware Description Language".

VHDL is the VHSIC Hardware Description Language. VHSIC is an abbreviation for Very High Speed Integrated Circuit.

It can describe the behaviour and structure of electronic systems, but is particularly suited as a language to describe the structure and behaviour of digital electronic hardware designs, such as ASICs and FPGAs as well as conventional digital circuits. VHDL is an international standard, regulated by the IEEE. Simulation and synthesis are the two main kinds of tools which operate on the VHDL language.

VHDL allows designs to be described using any methodology - top down, bottom up or middle out! VHDL can be used to describe hardware at the gate level or in a more abstract way.

vhdl-v stands for vhsic...that is very high speed integrated circuit...and hdl means hardware description language

Introduction to VHDL

Full form :-

Very high-speed integrated circuit hardware description language

INTRODUCTION:

VHDL stands for very high-speed integrated circuit hardware description language. Which is one of the programming language used to model a digital system by dataflow, behavioral and structural style of modeling. This language was first introduced in 1981 for the department of Defense (DoD) under the VHSIC programe. In 1983 IBM, Texas instruments and Intermetrics started to develop this language. In 1985 VHDL 7.2 version was released. In 1987 IEEE standardized the language.

http://www.electronicsgyan.com/introvhdl.aspx

Verilog is a hardware description language used to model electronic systems.