Show that a JK flip-flop can be converted to a D-Flip-flop with an inverted between the J and K inputs.?

Answer 1

---- The output of JK flip flop :

J K Q(t+1)

---- 0 0 Q(t)

0 1 0

1 0 1

1 1 Q'(t)

----

the excitation table becomes:

Q(t) Q(t+1) J K

----

0 0 0 X

0 1 1 X

1 0 X 1

1 1 X 0 where X represents "don't care"

----

The out put of D flip Flop is:

Q(t+1) D

---- 0 0

1 1

---- Using MAP method, we find the function F

0 1

---- 0 X

1 1 X

----

F= J+K'

Therefore the JK flip flop becomes a D flip flop with an inverter paced just before the K entrance.

I would have shown you more if this site allow graphics!

Answer 2

A JK Flip Flop can be easily converted to a D flip flop by simply joining the J input and K input before it enters it's respective Logical AND Gate and inserting an inverter (a logical NOT Gate) in between them.

Answer 3

just recall the basic SR latch with R and S as inputs, now if you multiply these inputs with clock pulse and send them new inputs instead of the previous S and R the so called formed circuit is called clocked SR flip-flop .

previously the inputs were S and R

now the inputs would be (CP.S) and (CP.R)

charecterstic table of clocked SR flip-flop

Q S R Q(t+1)

0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 indeterminate state(means this condition S=R=1 is never used)

1 0 0 1

1 0 1 0

1 1 0 1

1 1 1 indeterminate state(means this condition S=R=1 is never used)

it is very easy if u get the clocked SR flip-flop circuit diagram using NAND gates.

In this diagram just invert one the S/R inputs before multiplying them to the clock pulse

previously the inputs would be (cp.S) and (CP.R)

now they will be (CP.S) and (CP.S')

chaercterstic table for D flip-flop

Q D Q(t+1)

0 0 0

0 1 1

1 0 0

1 1 1

note:- you can verify this by placing the either R=S' or S=R' in the above truth table for SR clocked flip-flop

Answer 4

Simply invert Q and put in D an and add an input for each of the first 2 nand gates.