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You cannot make a NAND gate with only AND gates. An inverter is also required.
9,to implement a half adder 5 nand gates and for a full adder,another xor gate is required consisting of 4 nand gates. thus a total of 9 nand gates are required for a full adder.
for a half adder
sum = a (ex-or) b
carry = aXb
for a(ex-or)b ....6 nor gates are used
and for aXb 2 nor gates are used
totally 8 nor gates are used
12 NOR gates are required to implement full adder
more logic gates are used instead
by the procedure design a half subtractor design a logic ciruit to add two numbers with five bits each drawthe logic diagram of afull adder using using NAND gates only ?
NMOS PLA is a Programmable Logic Array which is designed by employing NMOS technology i.e. by employing nmos transistors to realize the required gates of PLA. PLA is a combination AND gates and OR gates to produced sum of products terms needed for realizing the required combinational logic. It consists of an array of AND gates followed by OR plane. the connections to the AND and OR inputs can be programmed based on our needs.
A logic gate composed only of diodes and resistors. The only types are AND gates and OR gates. However the number of layers of logic that can be implemented are severely limited due to losses in these gates.
9,to implement a half adder 5 nand gates and for a full adder,another xor gate is required consisting of 4 nand gates. thus a total of 9 nand gates are required for a full adder.
12 NOR gates are required to implement full adder
4
You cannot design a full adder using only OR gates. You also need AND gates. Typically, this can be done with just NAND gates.
i have the same question. please some1 answer it...
12
more logic gates are used instead
A: two
4 as a minimum, but you can use more if you really want to.
A&B = ((A&B)')' So two, it would go a - | ==NAND--=NAND-- b - | By using two NAND gates back-to-back, you can create a normal AND gate.
ab+bc
As such an OR gate should do the job...but if the question is of using gates other than the simple OR, it should be a combo of NOR and NOT gates; where-in, the NOT gate comes after the NOR gate. Factfully speaking: The output of a NOR gate when fed to a NOT gate shall give you an OR gate. cheers :) Anish Murthy Airpula, RF Design Engineer (F.A.E) Ceramic & Microwave Products Group, Dover Corporation Inc, United States of America