This classification was done by Wolfgang Handler. This classification mainly identifies the parallelism degree and pipelining degree built inside the hardware structure of the computer. Wolfgang Handler considers parallel - pipeline processing t sub system levels:
1. Process Control Unit(PCU)
2. Arithematic Logic Unit(ALU)
3. Bit - Level Circuit(BLU)
Each PCU Corresponds to one CPU. The ALU is considered as an element much smaller than a central processor and mucher lower features than a processor, working under the control of the processor. ALU is generally used to do arithematic and logical caliculations. In general there are many ALUs in a system, working parallely to increase the speed of the system. The BLC corresponds to the combinational logic circuitry needed to perform the bit operations on the ALU.
The computer system can be characterized by a triple containing six independent entities given below:
T(C) = <K * K', D * D', W * W'>
K = Number of processors within the computer.
K'= Number of PCUs that can be pipelined.
D = Number of ALUs under the control of one PCU.
D'= Number of ALUs that can be pipelined.
W = Word length of ALU.
W'= Number of pipelined stages in all ALUs.
I guess this will satisfy your need.