What is VHDL program for 4 to 16 decoder?

Answer 1

entity decoder3x8 is

port ( ctrl : in std_logic_vector (2 downto 0);

z : out std_logic_vector (7 downto 0) );

end decoder3x8;

architecture dec3x8_Dflow of decoder3x8 is

begin

z <= "00000001" when ctrl = "000" else

"00000010" when ctrl = "001" else

"00000100" when ctrl = "010" else

"00001000" when ctrl = "011" else

"00010000" when ctrl = "100" else

"00100000" when ctrl = "101" else

"01000000" when ctrl = "110" else

"10000000" ;

end dec3x8_Dflow;

-- the above code is dataflow modelling...still other modelling, ie structural and

--sequential

Answer 2

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity dec2to4df is

Port ( en1 : in STD_LOGIC;

a : in STD_LOGIC_VECTOR (1 downto 0);

z : out STD_LOGIC_VECTOR (3 downto 0));

end dec2to4df;

architecture df of dec2to4df is

begin

z(0)<= (not (en1))and(not a(1)) and (not a(0));

z(1)<= (not (en1))and (not a(1)) and a(0) ;

z(2)<= (not (en1))and a(1) and (not a(0));

z(3)<= (not (en1))and a(1) and a(0);

end df;

Answer 3

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity dec3to8 is

port(G1,G2a_l,G2b_l:in std_logic;

A: in STD_LOGIC_VECTOR(2 downto 0);

Y: out STD_LOGIC_VECTOR(0 to 7));

end dec3to8;

architecture behv of dec3to8 is

signal y_l:STD_LOGIC_VECTOR(0 to 7);

signal G:STD_LOGIC;

begin

process(G1,G2a_l,G2b_l,A,G)

begin

G<=(G1 and (not(G2a_l)) and (not(G2b_l)));

case A is

when "000"=>Y_l <= "01111111";

when "001"=>y_l <= "10111111";

when "010"=>y_l <= "11011111";

when "011"=>y_l <= "11101111";

when "100"=>y_l <= "11110111";

when "101"=>y_l <= "11111011";

when "110"=>y_l <= "11111101";

when "111"=>y_l <= "11111110";

when others=>y_l<= "11111111";

end case;

if (G='1') then y<=not(y_l);

else

y<="00000000";

end if;

end process;

end behv;

Answer 4

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity dec4to16 is

Port ( en : in STD_LOGIC;

i : in STD_LOGIC_VECTOR (3 downto 0);

y : out STD_LOGIC_VECTOR (15 downto 0));

end dec4to16;

architecture struct of dec4to16 is

signal n1,n2,n3,n4,n5:std_logic;

signal s:std_logic_vector(3 downto 0);

component dec2to4

Port ( en1 : in STD_LOGIC;

a : in STD_LOGIC_VECTOR (1 downto 0);

z : out STD_LOGIC_VECTOR (3 downto 0));

end component;

component notg

Port ( p : in STD_LOGIC;

q : out STD_LOGIC);

end component;

begin

u1:notg port map (en,n1);

u2:dec2to4 port map (n1,i(3 downto 2),s(3 downto 0));

u3:notg port map(s(3),n2);

u4:notg port map(s(2),n3);

u5:notg port map(s(1),n4);

u6:notg port map(s(0),n5);

u7:dec2to4 port map(n2,i(1 downto 0),y(15 downto 12));

u8:dec2to4 port map(n3,i(1 downto 0),y(11 downto 8));

u9:dec2to4 port map(n4,i(1 downto 0),y(7 downto 4));

u10:dec2to4 port map(n5,i(1 downto 0),y(3 downto 0));

end struct;