What is VHDL program for 8 bit priority encoder?

Answer 1

entity priorityenc is

Port ( EI_L : in STD_LOGIC;

I_L : in STD_LOGIC_VECTOR (7 downto 0);

A_L : out STD_LOGIC_VECTOR (2 downto 0);

E0_L : out STD_LOGIC;

GS_L : out STD_LOGIC);

end priorityenc;

architecture Behavioral of priorityenc is

signal EI: std_logic;

signal I: std_logic_vector(7 downto 0);

signal E0, GS: std_logic;

signal A: std_logic_vector(2 downto 0);

begin

process (EI_L , I_L, EI, E0, GS, I, A)

variable j: INTEGER range 7 downto 0;

begin

EI <= not EI_L; -- convert Input

I <= not I_L; -- convert inputs

E0 <= '1';

GS <='0';

A <= "000";

if(EI) ='0' then E0 <= '0';

else for j in 7 downto 0 loop

if I(j) ='1'

then GS<='1';

E0 <= '0';

A<= CONV_STD_LOGIC_VECTOR(j,3);

exit;

end if;

end loop;

end if;

E0_L <= not E0; -- convert output

GS_L <= not GS; -- convert output

A_L <= not A; -- convert outputs

end process;

end Behavioral;