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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ha is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

s : out STD_LOGIC;

c : out STD_LOGIC);

end ha;

architecture Behavioral of ha is

signal sel:std_logic_vector(1 downto 0);

begin

process(a,b)

begin

sel(1)<=a; sel(0)<=b;

case sel is

when "00"=> s<='0';c<='0';

when "01"=> s<='1';c<='0';

when "10"=> s<='1';c<='0';

when "11"=> s<='0';c<='1';

when others=> null;

end case;

end process ;

end Behavioral;

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