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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mpadd is
port ( a : in std_logic_vector(31 downto 0);
b : in std_logic_vector(31 downto 0);
y : out std_logic_vector(31 downto 0)
);
end mpadd;
architecture mpadd of mpadd is
return std_logic_vector is
Function to_integer(x:in std_logic_vector(6 downto 0))
return integer is
variable sum :integer:=0;
variable Temp :Std_logic_vector(6 downto 0);
begin
temp:=x;
xxx: for i in 0 to 6 loop
if (temp(i)='1')then
sum:=sum+2**i;
else
Sum:=Sum;
end if;
end loop;
return sum;
end function;
variable MaIn : std_logic_vector(22 downto 0); -- Internal Register
variable MbIn : std_logic_vector(22 downto 0); -- Internal Register
variable Ea,Eb : std_logic_vector(7 downto 0); -- Two Exponents including Sign
variable IR : std_logic_vector(22 downto 0); -- Resultant Mantissa
variable IE : std_logic_vector(6 downto 0); -- Resultant Exponent
variable Ns : integer; -- Number Of Shifts
variable Ma,Mb : std_logic_vector(22 downto 0); -- Mangitude Of Two mantissas
variable ES : std_logic; -- Sign Of Resulant Exponent
variable a,b : std_logic; -- Sign Of Two exponents
variable s1,s2 : std_logic; -- Sign Of Two mantissas
variable Sign : std_logic; -- Sign Of Resultant Mantissa
variable W,Z : std_logic_vector(1 downto 0);
variable X : std_logic_vector(31 downto 0); -- Final Result
begin
MaIn:=AccOut(22 downto 0);
MbIn:=Data(22 downto 0);
Ea :=AccOut(30 downto 23);
Eb :=Data(30 downto 23);
a :=AccOut(30);
b :=Data(30);
Z :=(a&b);
case Z is
when "00" => Mb:=MbIn;
Ma:=MaIn;
if((Ea(6 downto 0))<(Eb(6 downto 0))) then
NS:=to_integer(Eb(6 downto 0)-Ea(6 downto 0));
for x in 1 to NS loop
Ma := ('0' & Ma(22 downto 1));
end loop;
IE:=Eb(6 downto 0);
Es:=Eb(7)
elsif((Eb(6 downto 0))<(Ea(6 downto 0))) then
NS:=to_integer(Ea(6 downto 0)-Eb(6 downto 0));
for x in 1 to NS loop
Mb:=('0' & Mb(22 downto 1));
end loop;
IE:=Ea(6 downto 0);
Es:=Ea(7);
else
NS:=Ns;
Ma:=Ma;
Mb:=Mb;
IE:=IE;
ES:=Ea(7);
end if;
when "01" => Mb:=MbIn;
Ma:=MaIn;
NS:=to_integer(Ea(6 downto 0)+Eb(6 downto 0));
for x in 1 to NS loop
Mb:=('0' & Mb(22 downto 1));
end loop;
IE:=Ea(6 downto 0);
ES:=Ea(7);
when "10" => Mb:=MbIn;
Ma:=MaIn;
NS:=to_integer(Eb(6 downto 0)+Ea(6 downto 0));
for x in 1 to NS loop
Ma:=('0' & Ma(22 downto 1));
end loop;
IE:=Eb(6 downto 0);
ES:=Eb(7);
when "11" => Mb:=MbIn;
Ma:=MaIn;
if((Ea(6 downto 0))<(Eb(6 downto 0))) then
NS:=to_integer(Eb(6 downto 0)-Ea(6 downto 0));
for x in 1 to NS loop
Mb:=('0' & Mb(22 downto 1));
end loop;
IE:=Ea(6 downto 0);
ES:=Ea(7);
elsif((Eb(6 downto 0))<(Ea(6 downto 0))) then
NS:=to_integer(Ea(6 downto 0)-Eb(6 downto 0));
for x in 1 to NS loop
Ma:=('0' & Ma(22 downto 1));
end loop;
IE:=Eb(6 downto 0);
ES:=Eb(7);
else
NS:=Ns;
Ma:=Ma;
Mb:=Mb;
IE:=IE;
ES:=Ea(7);
end if;
when others => Null;
end case;
IR:=Ma+Mb;
s1:=Accout(31);
s2:=Data(31);
W :=(s1&s2);
case W is
when "00" => sign:='0';
when "11" => sign:='1';
when "01" => if(Ea>Eb) then
sign:='0';
elsif(Ea sign:='1'; elsif(Ea=Eb) then if(Ma>Mb) then sign:='0'; elsif(Ma sign:='1'; elsif(Ma=Mb) then sign:='0'; else sign:=sign; end if; else sign:=sign; end if; when "10" => if(Ea>Eb) then sign:='1'; elsif(Ea sign:='0'; elsif(Ea=Eb) then if(Ma>Mb) then sign:='1'; elsif(Ma sign:='0'; elsif(Ma=Mb) then sign:='0'; else sign:=sign; end if; else sign:=sign; end if; when others => null; end case; --***********Final Result After Addition*************************** X:=(sign & ES & IE & IR(22 downto 0)); return X; end function; begin process(a,b) begin y<=float_add(a,b); end process; end mpadd;
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vhdl code for ascending order of numbers
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karthika only know answer to this question
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