#include<stdio.h>
#include<conio.h>
int a[25],n,i;
void maxheapify(int,int);
void buildmaxheap();
void main()
{
int temp;
clrscr();
printf("\n\t\t\t\tHEAP SORT");
printf("\n\t\t\t\t**** ****\n\n\n");
printf("\n Enter no of elements:");
scanf("%d",&n);
printf("\n Enter elements to be sorted\n\n");
for(i=1;i<=n;i++)
scanf("%d",&a[i]);
buildmaxheap();
for(i=n;i>=2;i--)
{
temp=h[1];
a[1]=a[i];
a[i]=temp;
maxheapify(1,i-1);
}
printf("\n SORTED ELEMENT\n\n");
for(i=1;i<=n;i++)
printf("%d\n",a[i]);
getch();
}
void buildmaxheap()
{
int i;
for(i=n/2;i>=1;i--)
maxheapify(i,n);
}
void maxheapify(int i,int n)
{
int j,element;
j=2*i;
element=a[i];
while(j<=n)
{
if((j<n)&&(a[j]<a[j+1]))
j=j++;
if(element>=a[j])
break;
a[j/2]=a[j];
j=2*j;
}
a[j/2]=element;
}
to implement operations on binary heap in c
123
types of sorting in c language are: insertion sort selection sort bubble sort merge sort two way merge sort heap sort quick sort
yes we can do it,in c
Memory Organization for a process -------------------------------------------- CODE SEGMENT: contains executable code DATASEGMENT:contains static and global variable HEAP SEGMENT:Dynamically allocated variables will be in heap STACK SEGMENT:For local or automatic variables PREM G premgnath@gmail.com
eccount c
ram have divided into five part a) heap b)satck c)code d)global e) unpatition space
Below code can implement NOT gate in VHDL. The code is written in data flow model. Library ieee; use ieee.std_logic_1164.all; Entity gates is port (a : in std_logic; c : out std_logic); end gates ; architecture and1 of gates is begin c<=not a; end and1;
Below code can implement AND gate in VHDL. The code is written in data flow model. Library ieee; use ieee.std_logic_1164.all; Entity gates is port (a,b : in std_logic; c : out std_logic); end gates ; architecture and1 of gates is begin c<=a and b; end and1;
Below code can implement NAND gate in VHDL. The code is written in behavioral model. Library ieee; use ieee.std_logic_1164.all; Entity gates is port (a,b : in std_logic; c : out std_logic); end gates ; architecture and1 of gates is begin process(a,b) Begin If (a=1 and b=1) then C<='0'; Else C<= '1'; End if; End process; End and1;
Below code can implement NAND gate in VHDL. The code is written in data flow model. Library ieee; use ieee.std_logic_1164.all; Entity gates is port (a,b : in std_logic; c : out std_logic); end gates ; architecture and1 of gates is begin c<=a nand b; end and1;
Main Memory (RAM).