What is the VHDL code for half adder dataflow?

Answer 1

Half adder is a combinational circuit which can add two bits. It contains two inputs and two outputs. The same is implemented in entity declaration of VHDL program.

The outputs are related to inputs as follows:

SUM output is obtained by XORing the inputs and CARRY output is obtained by ANDing the inputs i. e. multiplication.

The VHDL code for half adder using data flow model is given below:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity had is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

s : out STD_LOGIC;

c : out STD_LOGIC);

end had;

architecture df of had is

begin

s<= a xor b;

c<= a and b;

end df;