When j=1 an k=1 and the clock pulse signal which remain at logic 1, after the output have been complemented once will cause repeated and continue transmission of output. This situation is called "raised condition".
To avoid this undesirable operation, the clock pulse must have a time duration which is shorter then the propagation delay through the flip flop.
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J=SET K=RESET NOTE: JK FLIP FLOP IS NOTHING BUT AN ADVANCED VERSION OF THE SET-RESET()SR FLIP FLOP) SO, JK FLIP FLOP ALSO WORKS SOMEWHAT LIKE THE SR FLIP FLOP..... IS ACTUALLY THE LABORATORY TERM OF NUMBER 5 FLIP FLOP 5# J & K.
This webpage have a detailed instruction on how to convert a D flip flop to a JK flip flop:Link: http://www.play-hookey.com/digital/converting_ff_inputs.html
no indeterminate state
An sr flip-flop can be converted into a jk flip-flop by changing the forbidden state in the sr flip-flop so that the out put toggles instead when the s=r=1.
flip-flop latches is 2. SR and JK latch
tie inputs together
the advantage of JK flip-flop compared to clocked SR flip
When the inputs J and k of the JK flip-flop are set to 1, the output toggles.
The JK in JK flip flop stands for Jack Kilby who was the inventor of JK flip flop.His complete name was Jack St. Clair Kilby.
in SR flip flop when we have S=1 R=1 we get intermediate state In JK flip flop we eliminate the intermediate state by complement Q- ( J=1,K=1 Q+ = (Q-)') so we can say that JK flip flop is refinement of SR flip flop Amjad Al.Haqpani
The JK flip-flop is not better than an RS flip-flop...it's just different. The selection of one or the other depends on what you are trying to do in your digital circuit design.