What about Modern trend in semiconductor memory?
Today's memory and storage hierarchy consists of embedded SRAM
on the processor die and DRAM as main
memory on one side, and HDDs for high-capacity storage on the
other side. Flash memory, in the form of solidstate-
disks (SSD), has recently gained a place in between DRAM and
HDD, bridging the large gap in latency
(105 times) and cost (100 times) between them. However, the use
of Flash in applications with intense data
traffic, i.e., as main memory or cache, is still hampered by the
large performance gap in terms of latency between
DRAM and Flash (still 1000 times), and the low endurance of
Flash (104 - 105 cycles), which deteriorates with
scaling and more aggressive MLC functionality. MLC technology
has become the focus of the Flash vendors
because they target the huge consumer-electronics market, where
the low cost per gigabyte of MLC plays a very
important role, but it suffers from endurance and latency
issues, which could be problematic for enterprise-class
applications. For example, at the 32-nm technology node and 2
bits per cell, it is expected that the standard
consumer-grade MLC will offer a write/erase endurance of approx.
3,000 cycles, which clearly will not suffice
for enterprise-class storage applications. On the other hand, an
enterprise-grade MLC with higher cost per
gigabyte could offer a write/erase endurance of 104 to 3 104,
albeit with a slower programming latency of
approx. 1.6 ms. These limitations of the MLC technology
necessitate the use of more complex error-correction
coding (ECC) schemes and Flash management functions, which,
depending on the workload, could improve the
reliability and hide the latency issues to a certain extent- but
certainly not to full satisfaction.
Moreover, as we go down on the technology node, these issues
will be further aggravated, and new challenges
will have to be resolved. For example, the stringent
data-retention requirements, in particular for
enterprisestorage
systems, impose a practical limit for the thickness of the
tunnel oxide. Another challenge in the scaling
of floating-gate NAND is floating-gate interference. To resolve
this issue, a charge-trapping layer has been proposed
as an alternative technology to the floating gate [2]. In
general, it was believed for a long time that by
moving to charge-trapping storage it would be possible to scale
at least to the 22-nm lithography generation.
However, recently a very promising trend towards stacking memory
cells in three dimensions in what is called
3D memory technology has emerged, and leading NAND Flash memory
manufacturers are already pursuing it
[11]. Of course, this 3D memory technology will not truly have
an impact on reliability, endurance and latency,
but it will offer much larger capacities at even lower cost in
the future. For all these reasons, NAND Flash is not
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expected to become an SCM technology in general.
Scaling issues are also critical for other solid-state memories,
such as SRAM and DRAM. Specifically,
SRAM suffers from signal-to-noise-ratio degradation and 10x
leakage increase with every technology node, and
DRAM faces a continuous increase of the refresh current.
Hence, there is a large opportunity for new solid-state
nonvolatile memory technologies with "universal
memory" characteristics. These technologies should not only
extend the lifetime of existing memories, but
also revolutionize the entire memory-storage hierarchy by
bridging the gap between memory (fast, expensive,
volatile) and storage (slow, inexpensive, permanent). The
requirements of this new family of technologies
called SCM [1] are nonvolatility, solid-state implementation (no
moving parts), low write/read latency (tens to
hundreds of nanoseconds), high endurance (more than 108 cycles),
low cost per bit (i.e., between the cost per bit
of DRAM and Flash), and scalability to future technology
nodes.
Many new nonvolatile solid-state memory technologies have
recently emerged. The objective has not only
been to realize dense memory arrays and show a viable
scalability roadmap, but also to achieve a performance
superior to that of Flash memory in many aspects. The catalog of
new technologies is very long, and they may
be broadly categorized into charge-trap-based, capacitance-based
and resistance-based memories. Charge-trap
based memories are basically extensions of the current
floating-gate-based Flash and, while offering advantages
in reliability, suffer from the same drawbacks that afflict
Flash technology, namely, low endurance and slow
writing speeds. Capacitance-based memories, in particular
ferroelectric memories (FeRAM), exhibit practically
infinite cycling endurance and very fast read/write speeds, but
are hampered by short retention times and, even
more importantly, their limited scaling potential up to the
22-nm node [12].
Resistance-based memories encompass a very broad range of
materials, switching mechanisms and associated
devices. Following the International Technology Roadmap for
Semiconductors (ITRS), one may categorize
resistance-based memories into nanomechanical, spin torque
transfer, nanothermal, nanoionic, electronic effects,
macromolecular and molecular memories [12]. Of these
technologies, those that have received more attention
by the scientific community and the semiconductor industry and
are thus in a more advanced state of research
and/or development, are spin torque transfer, nanoionic and
thermal memories. We will take a closer look at
these technologies next.
Spin-torque transfer memory (STTRAM) [13]-[15] is an advanced
version of the magnetic random access
memory (MRAM) in which the switching mechanism is based on the
magnetization change of a ferromagnetic
layer induced by a spin-polarized current flowing through it.
The most appealing features of STTRAM are its
very high read/write speed, on the order of 10 ns or less, and
its practically unlimited endurance. Important challenges
are overcoming the small resistance range (between low and high
resistance), which limits the possibility
of MLC storage, and achieving adequate margins not only between
read and write voltages but also between
write and breakdown voltages for reliable operation, especially
at high speeds.
Nanoionic memories [16]-[21] are characterized by a
metal-insulator-metal (MIM) structure, in which the
"metal" typically is a good electrical conductor (possibly even
dissimilar on the two sides of the device) and
the "insulator" consists of an ion-conducting material. Typical
insulator materials reported so far include binary
or ternary oxides, chalcogenides, metal sulfides, and even
organic compounds. The basic switching mechanism
in nanoionic memories is believed to be the combination of ionic
transport and electrochemical redox reactions
[19]. Most of these technologies-with very few exceptions-are
still in a very early stage of research, with
many of their interesting features derived from projections or
extrapolations from limited experimental data. As
is generally known, the actual issues associated with a
particular technology will likely only manifest themselves
in large demonstration device test vehicles, so that it may well
be that the road to widespread adoption of
nanoionic memories is still a long one.
The best known thermal memory is phase-change memory (PCM). This
discussion focuses on PCM, mainly
because of the very large activity around it and the advanced
state of development it has reached, allowing
credible projections regarding its ultimate potential. The
active material in PCM is a chalcogenide, typically
involving at least two of the materials Ge, Sb and Te, with the
most common compound being Ge2Sb2Te5
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or, simply, GST. The active material is placed between two
electrically conducting electrodes. The resistance
switching is induced by the current flowing through the active
material, which causes a structural change of
the material due to Joule heating. Phase-change materials
exhibit two meta-stable states, namely, a (poly)-
crystalline phase of long-range order and high electrical
conductivity and an amorphous phase of short-range
order and low electrical conductivity. Switching to the
amorphous phase (the RESET transition) is accomplished
by heating the material above its melting temperature followed
by ultra-fast quenching, whereas the crystalline
phase (SET transition) is reached by heating the materials above
its crystallization temperature and subsequent
annealing. The RESET transition necessitates high current, but
this current has been shown to scale linearly with
the technology node as well as decrease significantly in
confined memory cell architectures . The RESET
transition is fast, typically less than 50 ns in duration,
whereas the SET transition is on the order of 100 ns,
although very fast materials exhibiting sub-20-ns switching
times have been reported .
PCM scores well in terms of most of the desirable attributes of
a SCM technology. In particular, it exhibits
very good endurance, typically exceeding 108 cycles, excellent
retention, and superb scalability to sub-20-nm
nodes and beyond. Most importantly, these characteristic numbers
have been measured on large prototype
devices and thus provide confidence regarding the true
performance of the memory technology. On a smallerscale
device level, PCM has been shown to possess all the necessary
characteristics of a SCM technology.
Specifically, sub-20-ns SET switching times have been reported
with doped SbTe materials [23]. Furthermore,
an impressive device has been fabricated at the 17-nm design
rule at 4F2 size, with further scaling prospects not
limited by lithography but only by the material film thickness .
The same device showed an extrapolated
cycling endurance exceeding 1015 cycles. The ultimate scaling
limits of phase change in chalcogenide materials
provide an indication regarding the future scaling of PCM. In a
recent study, GST films that are a mere 2 nm
thick have been shown to crystallize when surrounded by proper
cladding layers .
Apart from the necessary RESET current reduction and SET speed
improvement discussed above, a significant
challenge of PCM technology is a phenomenon known as
(short-term) resistance drift: The resistance of
a cell is observed to drift upwards in time, with the amorphous
and partially-amorphous states drifting more
than their crystalline counterparts. This drift is believed to
be of electronic nature, manifests itself as noise,
and seriously affects the reliability of MLC storage in PCM
because of the reduced sensing margin between
adjacent tightly-packed resistance levels. Therefore, effective
solutions of the drift issue are a key factor of the
cost competitiveness of PCM technology and thus of its
suitability as SCM.
In summary, PCM is the only one of numerous emerging memory
technologies that has evolved from the
basic research stage to the advanced development and late
prototyping stage without encountering any fundamental
roadblocks. Advanced prototype PCM chips that at least partially
meet the requirements for SCM
already exist today, and new and exciting device demonstrations
have shown tremendous potential for
further improvement. These developments render PCM the leading
technology candidate for SCM today, with
the potential to play an extended role in the memory and storage
hierarchy of future computing systems.
