What are the elements of bus design?

Answer 1

BUS TYPES:

· Bus channels can be separated into two general types, namely a dedicated and multiplexed. A bus line dedicated permanently assigned a function or a subset of physical computer components.

· As an example of dedication to the function is the use of separate dedicated address and data lines, which is a common thing for the bus.

· However, this is not important. For example, the address and data information can be transmitted through the same number of channels using control channel address is invalid. In the early transfer of data, address bus and address placed on a valid control activated. At this time, each module has a specific time period to copy the address and determine whether the address is a module located. Then address removed from the bus and the bus connection is used for reading or writing data transfer next. Methods use the same line for various purposes is known as time multiplexing.

· The advantage is time multiplexing requires fewer channels, which saves space and cost. The disadvantage is the need for a more complex circuit within each module. There's also a fairly large decrease in performance due to certain events that use the channels together cannot function in parallel.

· Physical dedication associated with the use of multiple buses, each bus it is connected with only a subset of the modules. A common example is the use of bus I / O to interconnect all I / O module, then this bus is connected to the main bus through a kind of adapter module I / O. The main advantage of physical dedication is a high throughput; because of the traffic congestion is only small data. The disadvantage is the increased size and cost of the system.

b) ARBITRATION METHOD:

In all systems except the simplest system, more than one module is required to control the bus. For example, an I / O module may be required to read or write directly to memory, without sending data to the CPU. Because at one point is just a unit that will successfully transmit data through the bus, then take a few method of arbitration. The various methods by and large can be classified as a method centralized and distributed methods. In the centralized method, a hardware device, known as bus controllers or arbitrary, is responsible for the allocation of time on the bus. Perhaps it is CPU device module shaped or a separate section.

In a distributed method, there is no central controller. Rather, each module consists of access control logic and modules work together to put on a bus together. In the second method of arbitration, the goal is to assign a device, the CPU or I / O module, acting as master. Then the master can initiate data transfer (e.g., read or write) by using other devices, which work as slave for this particular data exchange.

C) Bus timing:

The timing diagram example on the right describes the Serial Peripheral Interface (SPI) Bus. Most SPI master nodes have the ability to set the clock polarity (CPOL) and clock phase (CPHA) with respect to the data. This timing diagram shows the clock for both values of CPOL as well as the values for the two data lines (MISO & MOSI) for each value of CPHA. Note that when CPHA=1 then the data is delayed by one-half clock cycle.

SPI operates in the following way:

• The master determines an appropriate CPOL & CPHA value
• The master pulls down the slave select (SS) line for a specific slave chip
• The master clocks SCK at a specific frequency
• During each of the 8 clock cycles the transfer is full duplex:
• The master writes on the MOSI line and reads the MISO line
• • The slave writes on the MISO line and reads the MOSI line
• When finished the master can continue with another byte transfer or pull SS high to end the transfer

When a slave's SS line is high then both of its MISO and MOSI line should be high impedance so to avoid disrupting a transfer to a different slave. Prior to SS being pulled low, the MISO & MOSI lines are indicated with a "z" for high impedance. Also prior to the SS being pulled low the "cycle #" row is meaningless and is shown greyed-out.

Note that for CPHA=1 the MISO & MOSI lines are undefined until after the first clock edge and are also shown greyed-out before that.

A more typical timing diagram has just a single clock and numerous data lines