What are the five stages in DLX pipeline in computer architecturect?

Answer 1

DLX is a simple pipeline architecture for CPU. It is mostly used in universities as a model to study pipelining technique.

The architecture of DLX was chosen based on observations about most frequently used primitives in programs. DLX provides a good architectural model for study, not only because of the recent popularity of this type of machine, but also because it is easy to understand.

Like most recent load/store machines, DLX emphasizes A simple load/store instruction set

Design for pipelining efficiency

An easily decoded instruction set

Efficiency as a compiler target

Operations There are four classes of instructions: Load/Store

Any of the GPRs or FPRs may be loaded and stored except that loading R0 has no effect.

ALU Operations

All ALU instructions are register-register instructions.

The operations are :

- add

- subtract

- AND

- OR

- XOR

- shifts

Compare instructions compare two registers (=,!=,<,>,=<,=>).

If the condition is true, these instructions place a 1 in the destination register, otherwise they place a 0.

Branches/Jumps

All branches are conditional.The branch condition is specified by the instruction, which may test the register source for zero or nonzero.

Floating-Point Operations

- add

- subtract

- multiply

- divide

An Implementation of DLX

Implementing the instruction set requires the introduction of several temporary registers that are not part of the architecture.

Every DLX instruction can be implemented in at most five clock cycles. The five clock cycles are Instruction fetch cycle (IF)

Instruction decode/register fetch (ID)

Execution/Effective address cycle (EX)

Memory access/branch completion cycle (MEM)

Write-back cycle (WB)

Detailed description of each follows:

Instruction fetch cycle (IF):IR <- MEM[PC]

NPC <- PC +4

Operation:

- Send out the PC and fetch the instruction from memory into the instruction register (IR)

- increment the PC by 4 to address the next sequential instruction

- the IR is used to hold the instruction that will be needed on subsequent clock cycles

- the NPC is used to hold the next sequential PC (program counter)

Instruction decode/register fetch (ID):A <- Regs[IR6..10]

B <- Regs[IR11..15]

Imm <- ((IR16)16##IR16..31)

Operation:

- Decode the instruction and access the register file to read the registers.

- the output of the general-purpose registers are read into two temporary registers (A and B) for use in later clock cycles.

- the lower 16 bits of the IR are also sign-extended and stored into the temporary register IMM, for use in the next cycle.

- decoding is done in parallel with reading registers, which is possible because these fields are at a fixed location in the DLX instruction format. This technique is known as fixed-field decoding.

Execution/Effective address cycle (EX):

The ALU operates on the operand prepared in the prior cycle, performing one of four functions depending on the DLX instruction typeMemory reference: ALUOutput <- A +ImmOperation: The ALU adds the operands to form the effective address and places the result into the register ALUOutput

Register-Register ALU instruction: ALUOutput <- A opBOperation: The ALU performs the operation specified by the opcode on the value in register A and on the value in register B. The result is placed in the register ALUOutput.

Register- Immediate ALU instruction: ALUOutput <- A opImmOperation: The ALU performs the operation specified by the opcode on the value in register A and on the value in register Imm. The result is placed in the register ALUOutput.

ALUOutput <- NPC + Imm

Cond <- ( A op 0 )

Operation:

-The ALU adds the NPC to the sign-extended immediate value in Imm to compute the address of the branch target.

-Register A, which has been read in the prior cycle, is checked to determine whether the branch is taken.

- the comparison operation op is the relational operator determined by the branch opcode (e.g. op is "==" for the instruction BEQZ) Memory access/branch completion cycle (MEM):

The only DLX instructions active in this cycle are loads, stores, and branches. Memory reference: LMD <- Mem[ALUOutput] or Mem[ALUOutput] <- BOperation:

-Access memory if needed

- If the instruction is load , data returns from memory and is placed in the LMD (load memory data) register

- If the instruction is store, data from the B register is written into memory.

- In either case the address used is the one computed during the prior cycle and stored in the register ALUOutput

Branch: if (cond) PC <- ALUOutput

else PC <- NPCOperation:

- If the instruction branches, the PC is replaced with branch destination address in the register ALUOutput

- Otherwise, PC is replaced with the incremented PC in the register NPC

Write-back cycle (WB):Register-Register ALU instruction: Regs[IR16..20] <- ALUOutput Register-Immediate ALU instruction: Regs[IR11..15] <- ALUOutput Load instruction: Regs[IR11..15] <- LMDOperation:

- Write the result into the register file, whether it comes from the memory(LMD) or from ALU (ALUOutput)

- the register destination field is in one of two positions depending on the opcode