What does RISC mean?

Answer 1

Instruction Set. ________________________________________ Addressing modes. TBD ________________________________________ Data movement. LDS Loads data from D memory in to given register. The address is specified by a second register. The data read is sign extended if necessary to fill the destination register. Source data can be 8, 16, 32 or 64 bits wide (up to data width of processor variant). The width is specified by a trailing B, W, L and LL respectively. LDZ As LDS but the data is not sign extended but zero padded to fill the destination register. LDIS Loads a constant into a given register. The four data widths of LDS are supported. Byte data is encoded within the instruction word, the others have the constant data read from the P memory in the locations following the instruction. LDIZ As LDIZ but the data is zero padded to fill the destination register. STR Stores the contents of a given register to the address in D memory given by a second register. PUSHREG As STR but always transfers the whole register contesnts and then increaments the destination address to the next appropriately sized location. POPREG As PUSHREG but the data is read from the D-memory into a register and the source address is decremented. COPY Copies the contents of one register to a second register. ________________________________________ ALU Instructions. ADD Adds the two given registers together and stores the result in the given destination register. ADDC Adds the two given registers together with the carry status bit and stores the result in the given destination register. SUB Subtracts a given register from another and stores the result in the given destination register. SUBC Subtracts a given register from another and the carry status bit and stores the result in the given destination register. CMP Compares two given registers. This is exactly the same as SUB, but the result of the calculation is not stored, just the status bits are updated. CMPC The same as CMP but the subtraction includes the carry status bit as in SUBC. This can be used to compare values greater than the width of the registers. AND Performs the bit wise AND upon the two registers given and puts the result in the destination register. OR Performs the bit wise OR upon the two registers given and puts the result in the destination register. XOR Performs the bit wise exclusive-OR upon the two registers given and puts the result in the destination register. NOT Performs the bit wise inversion of a register. NEG Negates the contents of a given register. Status Bits. Four status bits are maintained by the ALU. These are: • Zero(Z) Result is equal to zero. • Negative(N) Result is negative. • Carry(C) Result of an arithmetic operation produces a carry from the MSb. • Overflow(O) Result is too big for the destination register and has been truncated. ________________________________________ Jumps and Halts. Delay slots. Due to the program counter pipeline a delay slot is required after each instruction that changes the program counter. This delay slot is one instruction that is executed before the change to the program counter takes place. The delay slot instruction cannot be any instruction that changes the the program counter (can't handle nesting them) or any instruction that is not fully described in one word from the program memory. JMP Loads the program counter from the given register and execution continues from here after the delay slot instruction. JMPI As JMP but the new value of the program counter is provided in the P-data word following the instruction. JMPI.R As JMP but the new program counter value is calculated from the current value of the program counter added to the 12 bit value given (sign extended to 16 bits). JSR As JMP but the program counter is stored on the stack (so we can come back again with the RTS instruction). JSRI As JSR but the new value of the program counter is provided in the P-data word following the instruction. JSRI.R As JSR but the new program counter value is calculated from the current value of the program counter added to the 12 bit value given (sign extended to 16 bits). RTS Return from subroutine. The program counter is fetched from the stack and execution continues from here after the delay slot instruction. HALT Stops the program execution until awoken by an external 'wake up' signal or an interrupt. ________________________________________ Conditional Branches. The conditional branches all operate on the four status bits maintained by the ALU. These are masked by the four corresponding condition bits within the brach instructions and the branch is performed if any bits remain set after they are masked. The branch instructions use a delay slot for the next instruction to allow the program counter pipeline to catch up with a possible change. BRA Branch to address supplied by contents of the given register if the condition are met. BRA.R Branch to an address defined by the sum of the program counter and the immediate data if the condition is met. The immediate data is an 8 bit number that is sign extended to 16 bits before being added to the program counter. Note the program counter holds the address of the next instruction (the delay slot instruction) and it is to this value that the relative branch is performed. ________________________________________ Interrupts. LDIRQ Loads the interrupt handler register from the given register. This address is where the interrupt handler executes from. RTI Return from interrupt. The same as RTS but the processor also switches from using its shadow registers used during interrupts. ENIRQ Enable interrupts. DSIRQ Disable interrupts.

Answer 2

RISC (Reduced Instruction Set Computer) A computer architecture that reduces chip complexity by using simpler instructions. RISC compilers have to generate software routines to perform complex instructions that were previously done in hardware by CISC computers. In RISC, the microcode layer and associated overhead is eliminated. RISC keeps instruction size constant, bans the indirect addressing mode and retains only those instructions that can be overlapped and made to execute in one machine cycle or less. The RISC chip is faster than its CISC counterpart and is designed and built more economically.

Answer 3

RISC is a kind of microprocessor architecture that employ highly optimized, small set of instructions. RISC stands for Reduced Instruction Set Computer.

Answer 4

RISC (reduced instruction set computer) .