What is a FFT processor?

Answer 1

It is well known that the Fourier Transform (FT) has currently a key role in signal processing applications.

The FT is useful for frequency domain analysis of a signal, i.e. it transposes a signal from time domain into

frequency domain. Many application ranging from telecommunication, electric energy distribution systems, fail

prevention analysis and general signal processing use this transform as a tool for coding/decoding or spectrum

analysis of a signal. Because of the complexity of the processing algorithm of FT and its importance in signal

analysis, many people have been working on methods and application specific processor architecture for improving

the computation performance. To get that performance improvement, efforts have been done in two directions

mainly. One related to the algorithmic point of view[1,2,3], and the other based on ASIP architecture[2,4,5,6]. The

last one was pushed by VLSI technology evolution.

In this work, we present an architecture of a processor to perform FT analysis employing a datapath with

bit-serial and digit-serial integer operation. The objective of this work was get an area efficient architecture that

could be used as a co-processor with built in all resources necessary for an embedded application. Also, we guide our

design to have a simple input / output interface. The main difference between the architecture presented here and the

others rely on the usage of a datapath bit and digit serial oriented to process each butterfly highly parallel.

This paper is organized as follows. Section 2 provides a review of FT computation. Section 3 discusses the

proposed architecture, while section 4 presents some results, followed by conclusions and future work.