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Mixing memory of different types and latencies is not particularly a good idea. But you can often make them work together if you must and if you know what you are doing. If they are in the same bank, then you would likely have to override the detected memory settings in your CMOS. In that case, you'd usually have to use all the worst timings of the two (larger numbers). In this case, you'd have to use a latency of 5. This might be listed as CL or CAS if your motherboard will let you manually set the timings.

However, there is an exception. If you are also mixing speeds, you would have to use the slower speed. But if the faster memory has a higher latency, you might still get by with the lowest latency of the two. If you overclock memory, the latency gets worse, so if you underclock it, it gets better. The latency number is calculated by the rated speed, but it is measured by clock cycles, not by time. It would make more sense to end users to measure the latency by some time unit, but the memory controller has to know how many clock cycles to wait. You would likely need to convert the latency to nanoseconds. One formula is:

(CL/(Freq-in-MHZ) * 1000) = speed in ns

For DDR, remember to half the chip's label frequency. This formula will allow you to compare latencies, and if you reverse the process, you should be able to generate new compatible latencies if you must use the memory at a different frequency from the rated. If you must round latencies, go higher.

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