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When an instruction reaches a microprocessor it arrives at an internal block known as a "microcode sequencer" which is present in CISC architectures. This microcode sequencer then steps through a series of locations in the microcode ROM and issues control signals to the various registers, multiplexers, ALU, etc in the microprocessor.

RISC architectures lack this microcode sequencer, but have a similar construct known as a microcode translator or interpreter. Because RISC machines must complete execution in a single clock cycle, there aren't any "steps" to cycle through. Remember that RISC instructions are inherently more simple than CISC instructions.

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