Connectivity to the L-caches was handled by the BSB (Back-Side-Bus) for as long as cache has been implemented on-die. I'm unsure if this is the case in the most modern CPUs, but there is no integral reason to change this, so more than likely.
The Front Side Bus
CPU and L2 Cache
ATC (Advanced Transfer Cache) bus
Address Bus - Transmits memory addresses between the CPU and RAM.Data Bus - The bus that transfers data between CPU and RAM. Expansion Bus - The bus to which add-on adapter cards are connected in order to enhance the functionality on the PC. Video - The bus that transmits display information between the CPU and video circuitry.
atc bus
The Pentium Pro had both an L1 and an L2 cache on the CPU.
the CPU bus is the connection between the motherboard and the CPU. All data flows through different data bus.
Bus architecture is the pathway between the CPU and other peripherals. It is usually a shared input/output pathway. Bus is short for omnibus, which means, for all.
A serial bus.
Bus cycle is a single transaction between the main memory and the CPU.
The two primary types of bus lines on the motherboard that run between the CPU and the RAM sockets are the address bus and the data bus. The address bus is responsible for carrying the addresses of the data being accessed, allowing the CPU to specify which memory location it wants to read from or write to. The data bus, on the other hand, transfers the actual data between the CPU and the RAM. Together, these buses facilitate communication and data exchange between these critical components.
Your data busses sends information from component to component i.e. your FSB (front side bus)/system bus/internal bus communicates between your CPU and RAM, the faster it runs, the faster information is moved between your RAM and CPU giving your CPU quicker access to that data.