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The NAND gate has two or more inputs, and one output. This output is the complement of the AND of all the bits and will only be 0 if all the inputs are 1.

A NOT gate on the other hand has only 1 input, and the output is the complement of this input.


So to make a NAND gate into a NOT gate, we should tie (short, connect to same value) all the inputs of the NAND gate. At the output we would have the complement of the signal given at the tied inputs.


This way we have a NOT gate from a NAND gate.

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Q: When is that the NA ND logic gate can function as a NOT logic gate?
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