8 bit leading zero count vhdl program?

Answer 1

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity leadingzeros is

port (data : in std_logic_vector (7 downto 0);

zeros : out integer range 0 to 8);

end leadingzeros;

architecture Behavioral of leadingzeros is

begin

process (data)

variable temp : integer range 0 to 8;

begin

temp :=0;

for i in data'range loop

case data(i) is

when '0' => temp := temp +1;

when others => next;

end case;

zeros <= temp;

end loop;

end process;

end Behavioral;